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* Fix unused variables.Eli Friedman2013-09-103-6/+0
| | | | llvm-svn: 190448
* Remove unused functions.Eli Friedman2013-09-102-9/+0
| | | | llvm-svn: 190442
* ARM: Use the PICADD opcode calculated.Jim Grosbach2013-09-101-2/+6
| | | | | | | | | | | | | | We were figuring out whether to use tPICADD or PICADD, then just using tPICADD unconditionally anyway. Oops. A testcase from someone familiar enough with ELF to produce one would be appreciated. The existing PIC testcase correctly verifies the .s generated, but that doesn't catch this bug, which only showed up in direct-to-object mode. http://llvm.org/bugs/show_bug.cgi?id=17180 llvm-svn: 190417
* Remove unused private member in ARMAsmPrinter.cpp.Logan Chien2013-09-101-1/+1
| | | | | | | This commit removes the unused "AttributeItem" from ObjectAttributeEmitter. llvm-svn: 190412
* [SystemZ] Update README.Richard Sandiford2013-09-101-9/+5
| | | | llvm-svn: 190404
* [SystemZ] Add TM and TMYRichard Sandiford2013-09-104-14/+25
| | | | | | | | | | | | | | | | | | | | | | | The main complication here is that TM and TMY (the memory forms) set CC differently from the register forms. When the tested bits contain some 0s and some 1s, the register forms set CC to 1 or 2 based on the value the uppermost bit. The memory forms instead set CC to 1 regardless of the uppermost bit. Until now, I've tried to make it so that a branch never tests for an impossible CC value. E.g. NR only sets CC to 0 or 1, so branches on the result will only test for 0 or 1. Originally I'd tried to do the same thing for TM and TMY by using custom matching code in ISelDAGToDAG. That ended up being very ugly though, and would have meant duplicating some of the chain checks that the common isel code does. I've therefore gone for the simpler alternative of adding an extra operand to the TM DAG opcode to say whether a memory form would be OK. This means that the inverse of a "TM;JE" is "TM;JNE" rather than the more precise "TM;JNLE", just like the inverse of "TMLL;JE" is "TMLL;JNE". I suppose that's arguably less confusing though... llvm-svn: 190400
* [mips][msa] Removed unsupported dot product instructions (dotp_[su].b)Daniel Sanders2013-09-101-8/+0
| | | | | | The dotp_[su].b instructions never existed in any revision of the MSA spec. llvm-svn: 190398
* Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of ↵Vladimir Medic2013-09-101-0/+4
| | | | | | register when PFU is 32 bit. llvm-svn: 190397
* Remove obsolete code from MipsAsmParser.cpp.Vladimir Medic2013-09-101-22/+0
| | | | llvm-svn: 190396
* Revert r190366. It was breaking build bots.Bill Wendling2013-09-101-1/+1
| | | | llvm-svn: 190373
* Use a default value for the prologue's debug location.Bill Wendling2013-09-091-1/+1
| | | | llvm-svn: 190366
* Revert patches to add case-range support for PR1255.Bob Wilson2013-09-091-1/+1
| | | | | | | | | | | | | | | | | The work on this project was left in an unfinished and inconsistent state. Hopefully someone will eventually get a chance to implement this feature, but in the meantime, it is better to put things back the way the were. I have left support in the bitcode reader to handle the case-range bitcode format, so that we do not lose bitcode compatibility with the llvm 3.3 release. This reverts the following commits: 155464, 156374, 156377, 156613, 156704, 156757, 156804 156808, 156985, 157046, 157112, 157183, 157315, 157384, 157575, 157576, 157586, 157612, 157810, 157814, 157815, 157880, 157881, 157882, 157884, 157887, 157901, 158979, 157987, 157989, 158986, 158997, 159076, 159101, 159100, 159200, 159201, 159207, 159527, 159532, 159540, 159583, 159618, 159658, 159659, 159660, 159661, 159703, 159704, 160076, 167356, 172025, 186736 llvm-svn: 190328
* [mips] When double precision loads and stores are split into two i32 loads andAkira Hatanaka2013-09-091-3/+3
| | | | | | | stores, make sure the load or store that accesses the higher half does not have an alignment that is larger than the offset from the original address. llvm-svn: 190318
* [ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode.Joey Gouly2013-09-094-36/+121
| | | | | | | | | IT blocks can only be one instruction lonf, and can only contain a subset of the 16 instructions. Patch by Artyom Skrobov! llvm-svn: 190309
* A better way to silence the warning in MSVC (replaces r190304).Aaron Ballman2013-09-091-2/+1
| | | | llvm-svn: 190308
* Silencing a warning about control flow reaching the end of a non-void function.Aaron Ballman2013-09-091-0/+1
| | | | llvm-svn: 190304
* XCore handling of thread local loweringRobert Lytton2013-09-091-9/+94
| | | | | | | | | | | Fix XCoreLowerThreadLocal trying to initialise globals which have no initializer. Add handling of const expressions containing thread local variables. These need to be replaced with instructions, as the thread ID is used to access the thread local variable. llvm-svn: 190300
* XCore target: change to Sched::SourceRobert Lytton2013-09-091-1/+1
| | | | | | | This sidesteps a bug in PrescheduleNodesWithMultipleUses() which does not check if callResources will be affected by the transformation. llvm-svn: 190299
* XCore target: fix weak linkage attribute handlingRobert Lytton2013-09-091-1/+0
| | | | llvm-svn: 190298
* Generate compact unwind encoding from CFI directives.Bill Wendling2013-09-0916-342/+405
| | | | | | | | | | | | | | | We used to generate the compact unwind encoding from the machine instructions. However, this had the problem that if the user used `-save-temps' or compiled their hand-written `.s' file (with CFI directives), we wouldn't generate the compact unwind encoding. Move the algorithm that generates the compact unwind encoding into the MCAsmBackend. This way we can generate the encoding whether the code is from a `.ll' or `.s' file. <rdar://problem/13623355> llvm-svn: 190290
* Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the ↵Jiangning Liu2013-09-092-1/+696
| | | | | | | | following 26 instructions, SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL llvm-svn: 190288
* Add neverHasSideEffects=1 on a couple move instructions.Craig Topper2013-09-082-2/+2
| | | | llvm-svn: 190259
* Using popcount should check the popcount feature flag not the SSE41 feature ↵Craig Topper2013-09-081-2/+2
| | | | | | flag. llvm-svn: 190258
* [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index doubleAkira Hatanaka2013-09-076-74/+84
| | | | | | | | | | precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. llvm-svn: 190235
* [mips] Place parentheses around && to silence warning.Akira Hatanaka2013-09-071-3/+3
| | | | llvm-svn: 190234
* [mips] Add definition of instruction "drotr32" (double rotate right plus 32).Akira Hatanaka2013-09-072-0/+5
| | | | llvm-svn: 190232
* [mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fitAkira Hatanaka2013-09-076-46/+41
| | | | | | into a 5-bit or 6-bit field. llvm-svn: 190226
* [mips] Define "trap" as a pseudo instruction that turns into "break 0, 0".Akira Hatanaka2013-09-062-3/+11
| | | | llvm-svn: 190224
* [mips] Delete unused classes and defs.Akira Hatanaka2013-09-061-9/+1
| | | | llvm-svn: 190221
* [mips] Make "b" (unconditional branch) a pseudo. "b" is an assembly idiom, ↵Akira Hatanaka2013-09-064-16/+13
| | | | | | | | which is equivalent to "beq $zero, $zero, offset". llvm-svn: 190220
* [mips] Set instruction itineraries of loads, stores and conditional moves.Akira Hatanaka2013-09-063-33/+35
| | | | llvm-svn: 190219
* R600: Add support for LDS atomic subtractAaron Watry2013-09-063-0/+13
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 190200
* [mips][msa] IndentationDaniel Sanders2013-09-061-34/+34
| | | | llvm-svn: 190156
* [mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritanceDaniel Sanders2013-09-061-628/+628
| | | | | | | Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
* This patch adds support for microMIPS Multiply and Add/Sub instructions. ↵Vladimir Medic2013-09-062-5/+11
| | | | | | Test cases are included in patch. llvm-svn: 190154
* [mips][msa] Made the operand register sets optional for the VEC formatsDaniel Sanders2013-09-061-16/+9
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190153
* This patch adds support for microMIPS Move to/from HI/LO instructions. Test ↵Vladimir Medic2013-09-064-8/+44
| | | | | | cases are included in patch. llvm-svn: 190152
* [mips][msa] Made the operand register sets optional for the ELM_INSVE formatsDaniel Sanders2013-09-061-14/+10
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190151
* [mips][msa] Made the operand register sets optional for the 3RF_4RF formatDaniel Sanders2013-09-061-14/+14
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190150
* This patch adds support for microMIPS Move Conditional instructions. Test ↵Vladimir Medic2013-09-064-8/+33
| | | | | | cases are included in patch. llvm-svn: 190148
* [mips][msa] Made the operand register sets optional for the 3RF formatsDaniel Sanders2013-09-061-132/+72
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190146
* [mips][msa] Made the operand register sets optional for the 3R_4R formatDaniel Sanders2013-09-061-30/+22
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190145
* This patch adds support for microMIPS disassembler and disassembler make ↵Vladimir Medic2013-09-062-17/+93
| | | | | | check tests. llvm-svn: 190144
* [mips][msa] Made the operand register sets optional for the 2RF formatDaniel Sanders2013-09-061-59/+39
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190143
* [mips][msa] Made the operand register sets optional for the I8 formatDaniel Sanders2013-09-061-21/+12
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190142
* [mips][msa] Made the operand register sets optional for the I5 and SI5 formatsDaniel Sanders2013-09-061-74/+46
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190141
* [mips][msa] Made the operand register sets optional for the BIT_[BHWD] formatsDaniel Sanders2013-09-061-104/+60
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190140
* [SystemZ] Tweak integer comparison codeRichard Sandiford2013-09-066-121/+122
| | | | | | | | | | | | | | | | | | | The architecture has many comparison instructions, including some that extend one of the operands. The signed comparison instructions use sign extensions and the unsigned comparison instructions use zero extensions. In cases where we had a free choice between signed or unsigned comparisons, we were trying to decide at lowering time which would best fit the available instructions, taking things like extension type into account. The code to do that was getting increasingly hairy and was also making some bad decisions. E.g. when comparing the result of two LLCs, it is better to use CR rather than CLR, since CR can be fused with a branch while CLR can't. This patch removes the lowering code and instead adds an operand to integer comparisons to say whether signed comparison is required, whether unsigned comparison is required, or whether either is OK. We can then leave the choice of instruction up to the normal isel code. llvm-svn: 190138
* [mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element sizeDaniel Sanders2013-09-061-16/+16
| | | | | | No functional change llvm-svn: 190134
* [mips][msa] Made the operand register sets optional for the 3R formatDaniel Sanders2013-09-061-460/+280
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190133
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