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* Move single letter 'P' prefix out of multiclass now that tablegen allows ↵Craig Topper2012-12-271-86/+85
| | | | | | defm to start with #NAME. This makes instruction names more searchable again. llvm-svn: 171141
* Add hasSideEffects=0 to some shift and rotate instructions. None of which ↵Craig Topper2012-12-271-1/+5
| | | | | | are currently used by code generation. llvm-svn: 171137
* Mark the divide instructions as hasSideEffects=0.Craig Topper2012-12-271-0/+2
| | | | llvm-svn: 171136
* Add hasSideEffects=0 to CMP*rr_REV.Craig Topper2012-12-271-0/+1
| | | | llvm-svn: 171130
* Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC ↵Craig Topper2012-12-271-19/+43
| | | | | | instructions. Shouldn't change any functionality since they don't have patterns to select them. llvm-svn: 171128
* Fix operands and encoding form for ARPL instruction. Register form had and ↵Craig Topper2012-12-261-2/+2
| | | | | | reversed. Memory form writes memory, but was marked as MRMSrcMem. llvm-svn: 171123
* Add hasSideEffects=0 to some atomic instructions.Craig Topper2012-12-261-1/+1
| | | | llvm-svn: 171122
* Mark the AL/AX/EAX forms of the basic arithmetic operations has never having ↵Craig Topper2012-12-261-43/+44
| | | | | | side effects. llvm-svn: 171121
* Mark all the _REV instructions as not having side effects. They aren't ↵Craig Topper2012-12-264-9/+10
| | | | | | really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier. llvm-svn: 171118
* Remove a special conditional setting of neverHasSideEffects if the ↵Craig Topper2012-12-261-4/+3
| | | | | | instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns. llvm-svn: 171117
* Merge still more SSE/AVX instruction definitions.Craig Topper2012-12-261-43/+15
| | | | llvm-svn: 171103
* Merge more SSE/AVX instruction definitions.Craig Topper2012-12-261-129/+49
| | | | llvm-svn: 171102
* Fix 80 column violation.Craig Topper2012-12-261-2/+2
| | | | llvm-svn: 171097
* Fix class name in comment.Craig Topper2012-12-261-1/+1
| | | | llvm-svn: 171096
* Merge SSE/AVX PCMPEQ/PCMPGT instruction definitions.Craig Topper2012-12-261-62/+12
| | | | llvm-svn: 171095
* Remove 'v' from mnemonic to fix asm matching failures.Craig Topper2012-12-261-1/+1
| | | | llvm-svn: 171093
* Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction ↵Craig Topper2012-12-261-108/+42
| | | | | | definitions for a bunch of SSE2 integer arithmetic instructions. llvm-svn: 171092
* Reformat the docs.Nadav Rotem2012-12-261-20/+7
| | | | llvm-svn: 171091
* Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction ↵Craig Topper2012-12-261-30/+18
| | | | | | definitions for PAND/POR/PXOR/PANDN llvm-svn: 171087
* Merge an AVX/SSE 256-bit and 128-bit multiclass.Craig Topper2012-12-261-26/+15
| | | | llvm-svn: 171086
* Mark VANDNPD/VANDNPDS as not commutable.Craig Topper2012-12-261-1/+2
| | | | llvm-svn: 171085
* Remove alignment from a bunch more VEX encoded operations in the folding tables.Craig Topper2012-12-261-47/+47
| | | | llvm-svn: 171082
* Remove alignment from folding table for VMOVUPD as an unaligned instruction ↵Craig Topper2012-12-261-1/+1
| | | | | | it shouldn't require alignment... llvm-svn: 171081
* Remove alignment requirements from (V)EXTRACTPS. This instruction does ↵Craig Topper2012-12-261-2/+2
| | | | | | 32-bit stores which aren't required to be aligned on SSE or AVX. llvm-svn: 171080
* Remove alignment requirement from VCVTSS2SD in folding tables. Reverting ↵Craig Topper2012-12-261-2/+2
| | | | | | r171049. This instruction doesn't require alignment. llvm-svn: 171078
* Expand PPC64 atomic load and storeHal Finkel2012-12-251-0/+2
| | | | | | | | Use of store or load with the atomic specifier on 64-bit types would cause instruction-selection failures. As with the 32-bit case, these can use the default expansion in terms of cmp-and-swap. llvm-svn: 171072
* X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use ↵Benjamin Kramer2012-12-251-6/+4
| | | | | | of and commutativity. llvm-svn: 171064
* X86: Custom lower <2 x i64> eq and ne when SSE41 is not available.Benjamin Kramer2012-12-251-2/+24
| | | | | | | pcmpeqd, pshufd, pshufd, pand is cheaper than unpack + cmpq, sbbq, cmpq, sbbq + pack. Small speedup on loop-vectorized viterbi (-march=core2). llvm-svn: 171063
* VCVTSS2SD requires a strict alignment. Thanks Elena.Nadav Rotem2012-12-251-2/+2
| | | | llvm-svn: 171049
* Quiet gcc's -Wparenthesis warning. No functionality change.Nick Lewycky2012-12-241-1/+1
| | | | llvm-svn: 171044
* Use a std::string rather than a dynamically allocated char* buffer.Benjamin Kramer2012-12-242-21/+6
| | | | | | | | | | | | | This affords us to use std::string's allocation routines and use the destructor for the memory management. Switching to that also means that we can use operator==(const std::string&, const char *) to perform the string comparison rather than resorting to libc functionality (i.e. strcmp). Patch by Saleem Abdulrasool! Differential Revision: http://llvm-reviews.chandlerc.com/D230 llvm-svn: 171042
* CostModel: We have API for checking the costs of known shuffles. This patch addsNadav Rotem2012-12-241-1/+2
| | | | | | support for the insert-subvector and extract-subvector kinds. llvm-svn: 171027
* Some x86 instructions can load/store one of the operands to memory. On SSE, ↵Nadav Rotem2012-12-241-260/+260
| | | | | | | | | this memory needs to be aligned. When these instructions are encoded in VEX (on AVX) there is no such requirement. This changes the folding tables and removes the alignment restrictions from VEX-encoded instructions. llvm-svn: 171024
* Change the codegen Cost Model API for shuffeles. This patch removes the API ↵Nadav Rotem2012-12-241-1/+2
| | | | | | for broadcast and adds a more general API that accepts an enum of known shuffles. llvm-svn: 171022
* CostModel: Change the default target-independent implementation for findingNadav Rotem2012-12-231-3/+13
| | | | | | | | the cost of arithmetic functions. We now assume that the cost of arithmetic operations that are marked as Legal or Promote is low, but ops that are marked as custom are higher. llvm-svn: 171002
* whitespaceNadav Rotem2012-12-231-28/+0
| | | | llvm-svn: 170997
* Rename a function.Nadav Rotem2012-12-231-4/+4
| | | | llvm-svn: 170996
* Loop Vectorizer: Update the cost model of scatter/gather operations and makeNadav Rotem2012-12-232-9/+2
| | | | | | them more expensive. llvm-svn: 170995
* X86: Turn mul of <4 x i32> into pmuludq when no SSE4.1 is available.Benjamin Kramer2012-12-221-5/+29
| | | | | | | pmuludq is slow, but it turns out that all the unpacking and packing of the scalarized mul is even slower. 10% speedup on loop-vectorized paq8p. llvm-svn: 170985
* X86: Emit vector sext as shuffle + sra if vpmovsx is not available.Benjamin Kramer2012-12-221-8/+39
| | | | | | | Also loosen the SSSE3 dependency a bit, expanded pshufb + psra is still better than scalarized loads. Fixes PR14590. llvm-svn: 170984
* In some cases, due to scheduling constraints we copy the EFLAGS.Nadav Rotem2012-12-212-1/+21
| | | | | | | | | | | | The only way to read the eflags is using push and pop. If we don't adjust the stack then we run over the first frame index. This is not something that we want to do, so we have to make sure that our machine function does not copy the flags. If it does then we have to emit the prolog that adjusts the stack. rdar://12896831 llvm-svn: 170961
* [mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardwareAkira Hatanaka2012-12-213-54/+73
| | | | | | instructions. llvm-svn: 170956
* [mips] Refactor SYNC and multiply/divide instructions.Akira Hatanaka2012-12-213-54/+59
| | | | llvm-svn: 170955
* [mips] Refactor BAL instructions.Akira Hatanaka2012-12-212-10/+40
| | | | llvm-svn: 170954
* [mips] Fix encoding of BAL instruction. Also, fix assembler test case whichAkira Hatanaka2012-12-211-1/+1
| | | | | | was not catching the error. llvm-svn: 170953
* [mips] Refactor jump, jump register, jump-and-link and nop instructions.Akira Hatanaka2012-12-213-41/+50
| | | | llvm-svn: 170952
* [mips] Refactor load/store left/right and load-link and store-conditionalAkira Hatanaka2012-12-212-79/+52
| | | | | | instructions. llvm-svn: 170950
* [mips] Refactor load/store instructions.Akira Hatanaka2012-12-212-62/+34
| | | | llvm-svn: 170948
* [mips] Remove unnecessary isPseudo parameter.Akira Hatanaka2012-12-211-24/+16
| | | | llvm-svn: 170947
* [mips] Refactor LUI instruction.Akira Hatanaka2012-12-213-6/+17
| | | | llvm-svn: 170944
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