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* ARM Allow 'q' registers in VLD/VST vector lists.Jim Grosbach2011-10-281-4/+47
| | | | | | | | Just treat it as if the constituent D registers where specified. rdar://10348896 llvm-svn: 143167
* Remove the Alpha backend.Dan Gohman2011-10-2739-5315/+0
| | | | llvm-svn: 143164
* Add some NEON stores to the VLD decoding hook that were accidentally omitted ↵Owen Anderson2011-10-271-0/+4
| | | | | | previously. llvm-svn: 143162
* Also set addrmode6 alignment when align==size.Jakob Stoklund Olesen2011-10-271-1/+1
| | | | | | | Previously, we were only setting the alignment bits on over-aligned loads and stores. llvm-svn: 143160
* ARM isel for vld1, opcode selection for register stride post-index pseudos.Jim Grosbach2011-10-271-0/+4
| | | | llvm-svn: 143158
* Avoid partial CPSR dependency from loop backedges. rdar://10357570Evan Cheng2011-10-271-24/+43
| | | | llvm-svn: 143145
* Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix andKevin Enderby2011-10-272-3/+3
| | | | | | | not depend on In32BitMode. Use the sysexitq mnemonic for the version with the REX.W prefix and only allow it only In64BitMode. rdar://9738584 llvm-svn: 143112
* Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.Jim Grosbach2011-10-271-0/+6
| | | | | | rdar://10348844 llvm-svn: 143110
* Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.Jim Grosbach2011-10-271-1/+3
| | | | | | rdar://10348584 llvm-svn: 143108
* A branch predicated on a constant can just FastEmit an unconditional branch.Chad Rosier2011-10-271-0/+6
| | | | llvm-svn: 143086
* Rename NonScalarIntSafe to something more appropriate.Lang Hames2011-10-264-9/+9
| | | | llvm-svn: 143080
* Add a TODO comment. FastISel works by parsing each basic block from the bottomChad Rosier2011-10-261-0/+1
| | | | | | | | up. Thus, improving the support for compares is goodness because it increases the number of terminator instructions we can handle. This creates many more opportunities for target specific fast-isel. llvm-svn: 143079
* Factor a little more code into EmitCmp, which should have been done in the firstChad Rosier2011-10-261-23/+16
| | | | | | place. No functional change intended. llvm-svn: 143078
* Use EmitCmp in SelectBranch. No functional change intended.Chad Rosier2011-10-261-33/+6
| | | | llvm-svn: 143076
* Factor out an EmitCmp function that can be used by both SelectCmp andChad Rosier2011-10-261-18/+24
| | | | | | SelectBranch. No functional change intended. llvm-svn: 143072
* Thumb2 ldr pc-relative encoding fixes.Jim Grosbach2011-10-262-7/+16
| | | | | | | | | We were parsing label references to the i12 encoding, which isn't right. They need to go to the pci variant instead. More of rdar://10348687 llvm-svn: 143068
* Fixes an issue reported by -verify-machineinstrs.Rafael Espindola2011-10-262-6/+7
| | | | | | Patch by Sanjoy Das. llvm-svn: 143064
* ARM parse parenthesized expressions for label references.Jim Grosbach2011-10-261-0/+1
| | | | | | Partial fix for rdar://10348687. llvm-svn: 143063
* This commit introduces two fake instructions MORESTACK_RET andRafael Espindola2011-10-263-21/+39
| | | | | | | | | | | | MORESTACK_RET_RESTORE_R10; which are lowered to a RET and a RET followed by a MOV respectively. Having a fake instruction prevents the verifier from seeing a MachineBasicBlock end with a non-terminator (MOV). It also prevents the rather eccentric case of a MachineBasicBlock ending with RET but having successors nevertheless. Patch by Sanjoy Das. llvm-svn: 143062
* Make sure short memsets on ARM lower to stores, even when optimizing for size.Lang Hames2011-10-261-0/+2
| | | | llvm-svn: 143055
* Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern.Jim Grosbach2011-10-261-1/+1
| | | | llvm-svn: 143034
* Revert r142530 at least temporarily while a discussion is had on ↵James Molloy2011-10-261-5/+2
| | | | | | llvm-commits regarding exactly how much optsize should optimize for size over performance. llvm-svn: 143023
* Use a worklist to prevent the iterator from becoming invalidated because of ↵Bill Wendling2011-10-261-3/+4
| | | | | | the 'removeSuccessor' call. Noticed in a Release+Asserts+Check buildbot. llvm-svn: 143018
* Revert part of r142530. The patch potentially hurts performance especiallyEvan Cheng2011-10-261-3/+3
| | | | | | | on Darwin platforms where -Os means optimize for size without hurting performance. llvm-svn: 143002
* Corrects previously incorrect $sp change in MipsCompilationCallback.Bruno Cardoso Lopes2011-10-251-7/+7
| | | | | | | | The address for $sp, and addresses for sdc1/ldc1 must be 8-byte aligned Patch by Petar Jovanovic. llvm-svn: 142930
* ARM assembly parsing and encoding for VLD1 with writeback.Jim Grosbach2011-10-253-17/+33
| | | | | | Four entry register lists. llvm-svn: 142882
* Remove the Blackfin backend.Dan Gohman2011-10-2537-4415/+0
| | | | llvm-svn: 142880
* Remove the SystemZ backend.Dan Gohman2011-10-2437-6279/+0
| | | | llvm-svn: 142878
* Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.Jim Grosbach2011-10-243-4/+0
| | | | llvm-svn: 142877
* ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach2011-10-244-21/+33
| | | | | | Three entry register list variation. llvm-svn: 142876
* Don't crash on variable insertelement on ARM. PR10258.Eli Friedman2011-10-241-0/+11
| | | | llvm-svn: 142871
* ARMConstantPoolMBB::print should print BB number.Evan Cheng2011-10-241-0/+1
| | | | llvm-svn: 142867
* ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach2011-10-242-0/+38
| | | | | | One and two length register list variants. llvm-svn: 142861
* ARM refactor am6offset usage for VLD1.Jim Grosbach2011-10-245-71/+181
| | | | | | | | Split am6offset into fixed and register offset variants so the instruction encodings are explicit rather than relying an a magic reg0 marker. Needed to being able to parse these. llvm-svn: 142853
* Add support to the old JIT for acquire/release loads and stores on x86. ↵Eli Friedman2011-10-241-9/+24
| | | | | | PR11207. llvm-svn: 142841
* Fix a NEON disassembly case that was broken in the recent refactorings. As ↵Owen Anderson2011-10-241-6/+0
| | | | | | more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. llvm-svn: 142817
* Change this overloaded use of Sched::Latency to be an overloadedDan Gohman2011-10-241-2/+2
| | | | | | use of Sched::ILP instead, as Sched::Latency is going away. llvm-svn: 142813
* Remove the explicit request for "Latency" scheduling from MSP430,Dan Gohman2011-10-241-1/+0
| | | | | | as the Latency scheduler is going away. llvm-svn: 142811
* Thumb2 LDM instructions can target PC. Make sure to encode it.Jim Grosbach2011-10-241-8/+4
| | | | | | PR11220 llvm-svn: 142801
* Add X86 SARX, SHRX, and SHLX instructions.Craig Topper2011-10-231-18/+32
| | | | llvm-svn: 142779
* Add X86 RORX instructionCraig Topper2011-10-235-0/+36
| | | | llvm-svn: 142741
* Add X86 MULX instruction for disassembler.Craig Topper2011-10-231-0/+24
| | | | llvm-svn: 142738
* Remove some duplicate specifying of neverHasSideEffects and mayLoad from X86 ↵Craig Topper2011-10-221-5/+5
| | | | | | multiply instructions. llvm-svn: 142737
* Move various generated tables into read-only memory, fixing up const ↵Benjamin Kramer2011-10-223-11/+12
| | | | | | correctness along the way. llvm-svn: 142726
* Fix pr11193.Nadav Rotem2011-10-221-3/+0
| | | | | | | SHL inserts zeros from the right, thus even when the original sign_extend_inreg value was of 1-bit, we need to sra. llvm-svn: 142724
* The different flavors of ARM have different valid subsets of registers. CheckBill Wendling2011-10-221-3/+13
| | | | | | | that the set of callee-saved registers is correct for the specific platform. <rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2 llvm-svn: 142706
* Assembly parsing for 4-register sequential variant of VLD2.Jim Grosbach2011-10-213-36/+18
| | | | llvm-svn: 142704
* Assembly parsing for 2-register sequential variant of VLD2.Jim Grosbach2011-10-214-30/+46
| | | | llvm-svn: 142691
* Assembly parsing for 4-register variant of VLD1.Jim Grosbach2011-10-216-31/+38
| | | | llvm-svn: 142682
* Assembly parsing for 3-register variant of VLD1.Jim Grosbach2011-10-216-22/+37
| | | | llvm-svn: 142675
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