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* Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ↵Craig Topper2011-10-153-17/+46
| | | | | | because these are the first VEX encoded instructions to use the reg field as an opcode extension. llvm-svn: 142082
* The CELL backend cannot select patterns for vector trunc-store and shl on ↵Nadav Rotem2011-10-151-0/+9
| | | | | | v2i64; CellSPU/shift_ops.ll fails when promoting elements. llvm-svn: 142081
* ARM cannot select a pattern for trunc-store v4i8; /ARM/vrev.ll fails when ↵Nadav Rotem2011-10-151-0/+2
| | | | | | promoting elements. llvm-svn: 142080
* SmallVector -> arrayBenjamin Kramer2011-10-151-3/+3
| | | | llvm-svn: 142073
* Mark tADDrSPi as having side effects again.Jakob Stoklund Olesen2011-10-151-3/+3
| | | | | | | | | | | It really doesn't, but when r141929 removed the hasSideEffects flag from this instruction, it caused miscompilations. I am guessing that it got moved across a stack pointer update. Also clear isRematerializable after checking that this instruction is in fact never rematerialized in the nightly test suite. llvm-svn: 142030
* Thumb1 does not support dynamic stack realignment.Chad Rosier2011-10-151-0/+5
| | | | | | | | | | | rdar://10288916 is tracking this fix. In the past, instcombine and other passes were promoting alloca alignment past the natural alignment, resulting in dynamic stack realignment. Lang's work now prevents this from happening (LLVM commit r141599). Now that this really shouldn't happen report a fatal error rather than silently generate bad code. llvm-svn: 142028
* Mark registers as DEAD because they're really just clobbers.Bill Wendling2011-10-151-1/+1
| | | | llvm-svn: 142027
* Add missing correctness check to ARMTargetLowering::ReconstructShuffle. ↵Eli Friedman2011-10-141-0/+8
| | | | | | Fixes PR11129. llvm-svn: 142022
* Make sure that the register is in the register class before adding it as a ↵Bill Wendling2011-10-141-1/+3
| | | | | | machine op. llvm-svn: 142021
* Mark the invoke call instruction as implicitly defining the callee-saved ↵Bill Wendling2011-10-141-2/+31
| | | | | | | | | | registers. The callee-saved registers cannot be live across an invoke call because the control flow may continue along the exceptional edge. When this happens, all of the callee-saved registers are no longer valid. llvm-svn: 142018
* Fix a non-firing assert. Change:Richard Trieu2011-10-141-1/+1
| | | | | | | | assert("bad SymbolicOp.VariantKind"); To: assert(0 && "bad SymbolicOp.VariantKind"); llvm-svn: 142000
* A few 80-col violations.Evan Cheng2011-10-141-4/+8
| | | | llvm-svn: 141988
* Add an implementation of the CanLowerReturn function to the PPC backendHal Finkel2011-10-142-0/+17
| | | | llvm-svn: 141981
* Add f128 to datalayout string.Akira Hatanaka2011-10-141-2/+2
| | | | llvm-svn: 141978
* initial test commit (remove whitespace)Hal Finkel2011-10-141-2/+2
| | | | llvm-svn: 141972
* Revert r141932, r141936 and r141937.Akira Hatanaka2011-10-144-299/+1
| | | | llvm-svn: 141959
* Add X86 ANDN instruction. Including instruction selection.Craig Topper2011-10-144-2/+41
| | | | llvm-svn: 141947
* Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 ↵Craig Topper2011-10-145-5/+54
| | | | | | processor which is gcc's name for Haswell. llvm-svn: 141939
* Definition of function getMipsRegisterNumbering.Akira Hatanaka2011-10-141-0/+113
| | | | | | Patch by Jack Carter and Reed Kotler at Mips. llvm-svn: 141938
* Add definition of class MipsELFWriterInfo. Akira Hatanaka2011-10-143-0/+276
| | | | | | Patch by Jack Carter and Reed Kotler at Mips. llvm-svn: 141937
* Add missing relocation types.Akira Hatanaka2011-10-141-1/+3
| | | | | | Patch by Jack Carter and Reed Kotler at Mips. llvm-svn: 141936
* Fixup enumerations.Akira Hatanaka2011-10-141-0/+90
| | | | | | Patch by Jack Carter at Mips. llvm-svn: 141934
* Add more Mips relocation types.Akira Hatanaka2011-10-141-1/+21
| | | | | | Patch by Jack Carter at Mips. llvm-svn: 141932
* Ban rematerializable instructions with side effects.Jakob Stoklund Olesen2011-10-144-11/+13
| | | | | | | | | | TableGen infers unmodeled side effects on instructions without a pattern. Fix some instruction definitions where that was overlooked. Also raise an error if a rematerializable instruction has unmodeled side effects. That doen't make any sense. llvm-svn: 141929
* V_SET0 has no side effects.Jakob Stoklund Olesen2011-10-141-1/+1
| | | | | | | | | | TableGen will mark any pattern-less instruction as having unmodeled side effects. This is extra bad for V_SET0 which gets rematerialized a lot. This was part of the cause for PR11125, but the real bug was fixed in r141923. llvm-svn: 141924
* Fix undefined shift. Patch by Ahmed Charles.Eli Friedman2011-10-131-1/+1
| | | | llvm-svn: 141914
* Simplify assertion, and avoid undefined shift. Based on patch by Ahmed Charles.Eli Friedman2011-10-131-8/+1
| | | | llvm-svn: 141912
* Fix undefined shifts and abs in Alpha backend. Based on patch by Ahmed Charles.Eli Friedman2011-10-131-4/+3
| | | | llvm-svn: 141909
* Simplify and avoid undefined shift. Based on patch by Ahmed Charles.Eli Friedman2011-10-131-2/+1
| | | | llvm-svn: 141903
* SETEND is not allowed in an IT block.Owen Anderson2011-10-131-0/+1
| | | | llvm-svn: 141874
* Mark 'branch indirect' instruction as an indirect branch.Kalle Raiskila2011-10-131-2/+4
| | | | | | Not having it confused assembly printing of jumptables. llvm-svn: 141862
* More closely follow libgcc, which has code after the `ret' instruction toBill Wendling2011-10-131-5/+24
| | | | | | | release the stack segment and reset the stack pointer. Place the code in its own MBB to make the verifier happy. llvm-svn: 141859
* Revert r141854 because it was causing failures:Bill Wendling2011-10-134-52/+5
| | | | | | | | | | | | | | | http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101 --- Reverse-merging r141854 into '.': U test/MC/Disassembler/X86/x86-32.txt U test/MC/Disassembler/X86/simple-tests.txt D test/CodeGen/X86/bmi.ll U lib/Target/X86/X86InstrInfo.td U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86.td U lib/Target/X86/X86Subtarget.h llvm-svn: 141857
* Should not add instructions to a BB after a return instruction. The machine ↵Bill Wendling2011-10-131-1/+2
| | | | | | instruction verifier doesn't like this, nor do I. llvm-svn: 141856
* Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 ↵Craig Topper2011-10-134-5/+52
| | | | | | processor which is gcc's name for Haswell. llvm-svn: 141854
* Add 'implicit EFLAGS' to patterns for popcnt and lzcntCraig Topper2011-10-132-12/+23
| | | | llvm-svn: 141853
* ARM addrmode5 represents the 'U' bit of the encoding backwards.Jim Grosbach2011-10-121-14/+17
| | | | | | | The disassembler needs to use the AM5 factory methods instead of just building up the immediate directly. llvm-svn: 141819
* Thumb2 assembly parsing and encoding for LDC/STC.Jim Grosbach2011-10-123-99/+116
| | | | llvm-svn: 141811
* addrmode2 is gone from these, so no need for the reg0 operand.Jim Grosbach2011-10-121-24/+0
| | | | llvm-svn: 141794
* ARM parsing and encoding for the <option> form of LDC/STC instructions.Jim Grosbach2011-10-124-9/+84
| | | | llvm-svn: 141786
* 80 columns.Jim Grosbach2011-10-121-2/+1
| | | | llvm-svn: 141781
* Tidy up. Formatting.Jim Grosbach2011-10-121-2/+2
| | | | llvm-svn: 141780
* Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it.Akira Hatanaka2011-10-122-13/+5
| | | | llvm-svn: 141761
* Fix encoding of 32-bit integer instructions. Change names of operands and nodes.Akira Hatanaka2011-10-121-87/+108
| | | | | | Remove unused classes. llvm-svn: 141757
* Fix indent in comment.Nick Lewycky2011-10-121-1/+1
| | | | llvm-svn: 141749
* Fix -widen-vmovs liveness issues.Jakob Stoklund Olesen2011-10-121-3/+29
| | | | | | | | | | | | | | | | | | | | | | When widening a copy, we are reading a larger register that may not be live. Use an <undef> flag to tell the register scavenger and machine code verifier that we know the value isn't defined. We now widen: %S6<def> = COPY %S4<kill>, %D3<imp-def> into: %D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill> This also keeps the <kill> flag on %S4 so we don't inadvertently kill a live value in %S5. Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves the <undef> flag when converting VMOVD to VORR. llvm-svn: 141746
* Change name of class to ArithOverflowR.Akira Hatanaka2011-10-111-3/+3
| | | | llvm-svn: 141743
* Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logicalAkira Hatanaka2011-10-112-35/+19
| | | | | | instructions with two register operands derive from it. llvm-svn: 141742
* Fix comment.Akira Hatanaka2011-10-111-1/+1
| | | | llvm-svn: 141737
* Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bitAkira Hatanaka2011-10-112-43/+25
| | | | | | | arithmetic and logical instructions with three register operands derive from them. Fix instruction encoding too. llvm-svn: 141736
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