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* Reverting the commit 116986. It was breaking the build on llvm-x86_64-linux ↵Wesley Peck2010-10-2129-1833/+603
| | | | | | | | | though it compiles on OS X. I'll ensure that it builds on a linux machine before committing again. llvm-svn: 116991
* Revert r116983, which is breaking all the buildbots.Owen Anderson2010-10-213-38/+4
| | | | llvm-svn: 116987
* Major update of the MicroBlaze backend. The new features are:Wesley Peck2010-10-2129-603/+1833
| | | | | | | | | | | | | | | | | | | | 1. A delay slot filler that searches for valid instructions to fill the delay slot with. Previously NOPs would always be inserted into delay slots. 2. Support for MC based instruction printer added. 3. Support for MC based machine code generation and ELF file generation. ELF file generation does not yet completely work as much of the ELF support infrastructure is still x86/x86-64 specific. 4. General clean up of the MBlaze backend code. Much of the tablegen code has been cleanup and simplified. Bug Fixes: 1. Removed duplicate periods from subtarget feature descriptions. 2. Many of the instructions had bad machine code information in the tablegen files. Much of this has been fixed. llvm-svn: 116986
* X86: Add alloca probing to dynamic alloca on Windows. Fixes PR8424.Michael J. Spencer2010-10-214-23/+26
| | | | llvm-svn: 116984
* Add missing scheduling itineraries for transfers between core registers and ↵Evan Cheng2010-10-213-4/+38
| | | | | | VFP registers. llvm-svn: 116983
* Implement correct encodings for NEON vadd, both integer and floating point.Owen Anderson2010-10-211-6/+32
| | | | llvm-svn: 116981
* CodeGen-Windows: Only emit _fltused if a VarArg function is called with ↵Michael J. Spencer2010-10-211-1/+1
| | | | | | | | floating point args. This should be the minimum set of functions that could possibly need it. llvm-svn: 116978
* Custom lower f64 args passed in integer registers.Eric Christopher2010-10-211-0/+15
| | | | llvm-svn: 116977
* Fix Whitespace.Michael J. Spencer2010-10-203-138/+138
| | | | llvm-svn: 116972
* Add encoding for moving a value between two ARM core registers and a doubleworkBill Wendling2010-10-201-6/+28
| | | | | | extension register. llvm-svn: 116970
* Add encodings for movement between ARM core registers and single-precisionBill Wendling2010-10-202-33/+59
| | | | | | registers. llvm-svn: 116961
* Fix crash introduced in 116852. 8573915.Dale Johannesen2010-10-201-2/+3
| | | | llvm-svn: 116955
* Remove Synthesizable from the Type system; as MMX vectorDale Johannesen2010-10-201-1/+1
| | | | | | | types are no longer Legal on X86, we don't need it. No functional change. 8499854. llvm-svn: 116947
* Handle _GLOBAL_OFFSET_TABLE_ correctly.Rafael Espindola2010-10-201-0/+27
| | | | llvm-svn: 116932
* Remove remaining uses of ATTRIBUTE_UNUSED on variables, and delete threeChandler Carruth2010-10-201-2/+0
| | | | | | #includes in the process. llvm-svn: 116919
* Fix a TODO by removing some unnecesary copies.Eric Christopher2010-10-201-13/+5
| | | | llvm-svn: 116915
* Fix backwards conditional.Jim Grosbach2010-10-201-1/+1
| | | | llvm-svn: 116897
* Add dynamic realignment when rematerializing the base register.Jim Grosbach2010-10-201-0/+13
| | | | llvm-svn: 116886
* Nuke a commented out bit that got missed a while back.Jim Grosbach2010-10-191-1/+1
| | | | llvm-svn: 116883
* Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do anyJim Grosbach2010-10-196-13/+82
| | | | | | | setup they require. Use this for ARM/Darwin to rematerialize the base pointer from the frame pointer when required. rdar://8564268 llvm-svn: 116879
* Update comments to remove obsolete references.Jim Grosbach2010-10-191-6/+5
| | | | llvm-svn: 116863
* Enable using vdup for vector constants which are splat ofDale Johannesen2010-10-191-32/+17
| | | | | | | integers by default, and remove the controlling flag, now that LICM will hoist such vdup's. 8003375. llvm-svn: 116852
* Re-enable register pressure aware machine licm with fixes. Hoist() may haveEvan Cheng2010-10-194-0/+65
| | | | | | | erased the instruction during LICM so UpdateRegPressureAfter() should not reference it afterwards. llvm-svn: 116845
* Get rid of static constructors for pass registration. Instead, every pass ↵Owen Anderson2010-10-192-1/+6
| | | | | | | | | | | | | | | | | exposes an initializeMyPassFunction(), which must be called in the pass's constructor. This function uses static dependency declarations to recursively initialize the pass's dependencies. Clients that only create passes through the createFooPass() APIs will require no changes. Clients that want to use the CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h before parsing commandline arguments. I have tested this with all standard configurations of clang and llvm-gcc on Darwin. It is possible that there are problems with the static dependencies that will only be visible with non-standard options. If you encounter any crash in pass registration/creation, please send the testcase to me directly. llvm-svn: 116820
* Revert r116781 "- Add a hook for target to determine whether an instruction defDaniel Dunbar2010-10-194-65/+0
| | | | | | is", which breaks some nightly tests. llvm-svn: 116816
* Add lower argument and return of device functionChe-Liang Chiou2010-10-197-9/+275
| | | | llvm-svn: 116805
* X86: Add MS-CRT libcalls.Michael J. Spencer2010-10-191-0/+2
| | | | llvm-svn: 116801
* Fix Whitespace.Michael J. Spencer2010-10-192-26/+26
| | | | llvm-svn: 116800
* - Add a hook for target to determine whether an instruction def isEvan Cheng2010-10-194-0/+65
| | | | | | | | | | | "long latency" enough to hoist even if it may increase spilling. Reloading a value from spill slot is often cheaper than performing an expensive computation in the loop. For X86, that means machine LICM will hoist SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON instructions. - Enable register pressure aware machine LICM by default. llvm-svn: 116781
* Support alignment for NEON vld-lane and vst-lane instructions.Bob Wilson2010-10-191-0/+11
| | | | llvm-svn: 116776
* Added a few tweaks to the Intel Descriptor-table support instructions to allowKevin Enderby2010-10-192-0/+48
| | | | | | | word forms and suffixed versions to match the darwin assembler in 32-bit and 64-bit modes. This is again for use just with assembly source for llvm-mc . llvm-svn: 116773
* ARM encoding information for [SU]SAT* instructions.Jim Grosbach2010-10-181-14/+58
| | | | llvm-svn: 116768
* Revert r116220 - thus turning arm fast isel back on by default.Eric Christopher2010-10-181-3/+3
| | | | llvm-svn: 116762
* Don't recompute MachineRegisterInfo in the Optimize* method.Bill Wendling2010-10-182-6/+7
| | | | llvm-svn: 116750
* For Thumb2, try to use frame pointer references for stack slots even when aJim Grosbach2010-10-181-2/+10
| | | | | | base register is available. rdar://8525298 llvm-svn: 116729
* Produce ELF::R_386_GOTPC relocations.Rafael Espindola2010-10-181-0/+5
| | | | llvm-svn: 116728
* Added a handful of x86-32 instructions that were missing so that llvm-mc wouldKevin Enderby2010-10-183-1/+51
| | | | | | | | | | be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. llvm-svn: 116716
* ARM addrmode4 instructions (ldm, stm and friends) can't encode an immediateJim Grosbach2010-10-181-1/+2
| | | | | | | | offset for stack references. Make sure we take that into account when deciding whether to reserver an emergency spill slot for the register scavenger. rdar://8559625 llvm-svn: 116714
* Grammar tweak.Jim Grosbach2010-10-181-1/+1
| | | | llvm-svn: 116712
* Improve lowering of sext to i128 on SPU.Kalle Raiskila2010-10-181-2/+7
| | | | | | | | The old algorithm inserted a 'rotqmbyi' instruction which was both redundant and wrong - it made shufb select bytes from the wrong end of the input quad. llvm-svn: 116701
* Remove the check for invalid calling conventions. Testing shows that they'reEric Christopher2010-10-181-4/+1
| | | | | | working just fine. llvm-svn: 116698
* Lift arg promotion from the X86 backend. This should be unified at some point.Eric Christopher2010-10-181-3/+57
| | | | llvm-svn: 116694
* Now that we handle all allocas via a non-SP reg offset remove all of theEric Christopher2010-10-171-79/+39
| | | | | | special case handling for ARM::SP. llvm-svn: 116688
* Allow more load types to be materialized through the allocas.Eric Christopher2010-10-171-1/+1
| | | | llvm-svn: 116683
* Optimize GEP off of intermediate allocas.Eric Christopher2010-10-171-14/+46
| | | | llvm-svn: 116681
* Fix comment.Eric Christopher2010-10-171-1/+1
| | | | llvm-svn: 116680
* Turn on AddOperator folding in GEP.Eric Christopher2010-10-171-1/+1
| | | | llvm-svn: 116679
* Use the i12 immediate versions of the load instructions - they're handledEric Christopher2010-10-171-6/+6
| | | | | | more in the post-passes. llvm-svn: 116678
* Add a MCObjectFormat class so that code common to all targets that use aRafael Espindola2010-10-162-4/+32
| | | | | | | | | | | | single object format can be shared. This also adds support for mov zed+(bar-foo), %eax on ELF and COFF targets. llvm-svn: 116675
* X86-Windows: Emit an undefined global __fltused symbol when targeting WindowsMichael J. Spencer2010-10-161-0/+7
| | | | | | if any floating point arguments are passed to an external function. llvm-svn: 116665
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