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* [AMDGPU] Enable changing instprinter's behavior based on the per-functionKonstantin Zhuravlyov2016-09-273-132/+214
| | | | | | | | | | subtarget This is a prerequisite for coming waitcnt changes Differential Revision: https://reviews.llvm.org/D24939 llvm-svn: 282489
* [mips] Disable tail calls temporarilySimon Dardis2016-09-271-1/+1
| | | | | | | | | | Disable tail calls while the remaining bugs are fixed. Enable only for tests. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24912 llvm-svn: 282487
* [mips] Add rsqrt, recip for MIPSSimon Dardis2016-09-278-25/+77
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 282485
* [Power9] Builtins for ELF v.2 API conformance - back end portionNemanja Ivanovic2016-09-273-31/+78
| | | | | | | | | | | | | | | | This patch corresponds to review: https://reviews.llvm.org/D24396 This patch adds support for the "vector count trailing zeroes", "vector compare not equal" and "vector compare not equal or zero instructions" as well as "scalar count trailing zeroes" instructions. It also changes the vector negation to use XXLNOR (when VSX is enabled) so as not to increase register pressure (previously this was done with a splat immediate of all ones followed by an XXLXOR). This was done because the altivec.h builtins (patch to follow) use vector negation and the use of an additional register for the splat immediate is not optimal. llvm-svn: 282478
* [X86] Use std::max to calculate alignment instead of assuming RC->getSize() ↵Craig Topper2016-09-271-2/+2
| | | | | | will not return a value greater than 32. I think it theoretically could be 64 for AVX-512. llvm-svn: 282471
* [CodeGen] Add support for emitting .init_array instead of .ctors on FreeBSD.Davide Italiano2016-09-263-0/+15
| | | | | PR: 30494 llvm-svn: 282451
* [WebAssembly] Use the frame pointer instead of the stack pointerDerek Schuff2016-09-261-4/+9
| | | | | | | | | | | When we have dynamic allocas we have a frame pointer, and when we're lowering frame indexes we should make sure we use it. Patch by Jacob Gravelle Differential Revision: https://reviews.llvm.org/D24889 llvm-svn: 282442
* Add support for Code16GCCNirav Dave2016-09-261-20/+42
| | | | | | | | | | | | | [X86] The .code16gcc directive parses X86 assembly input in 32-bit mode and outputs in 16-bit mode. Teach parser to switch modes appropriately. Reviewers: dwmw2, craig.topper Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D20109 llvm-svn: 282430
* Add optimization bisect support to an optional Mips passAndrew Kaylor2016-09-261-0/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D19513 llvm-svn: 282428
* AMDGPU/SI: Don't crash on anonymous GlobalValuesTom Stellard2016-09-263-7/+14
| | | | | | | | | | | | | | Summary: We need to call AsmPrinter::getNameWithPrefix() in order to handle anonymous GlobalValues (e.g. @0, @1). Reviewers: arsenm, b-sumner Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D24865 llvm-svn: 282420
* [AArch64] Improve add/sub/cmp isel of uxtw forms.Geoff Berry2016-09-263-8/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't match the UXTW extended reg forms of ADD/ADDS/SUB/SUBS if the 32-bit to 64-bit zero-extend can be done for free by taking advantage of the 32-bit defining instruction zeroing the upper 32-bits of the X register destination. This enables better instruction selection in a few cases, such as: sub x0, xzr, x8 instead of: mov x8, xzr sub x0, x8, w9, uxtw madd x0, x1, x1, x8 instead of: mul x9, x1, x1 add x0, x9, w8, uxtw cmp x2, x8 instead of: sub x8, x2, w8, uxtw cmp x8, #0 add x0, x8, x1, lsl #3 instead of: lsl x9, x1, #3 add x0, x9, w8, uxtw Reviewers: t.p.northover, jmolloy Subscribers: mcrosier, aemerson, llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D24747 llvm-svn: 282413
* Add support to optionally limit the size of jump tables.Evandro Menezes2016-09-263-0/+10
| | | | | | | | | | | | | | | | | | | Many high-performance processors have a dedicated branch predictor for indirect branches, commonly used with jump tables. As sophisticated as such branch predictors are, they tend to have well defined limits beyond which their effectiveness is hampered or even nullified. One such limit is the number of possible destinations for a given indirect branches that such branch predictors can handle. This patch considers a limit that a target may set to the number of destination addresses in a jump table. Patch by: Evandro Menezes <e.menezes@samsung.com>, Aditya Kumar <aditya.k7@samsung.com>, Sebastian Pop <s.pop@samsung.com>. Differential revision: https://reviews.llvm.org/D21940 llvm-svn: 282412
* [AVR] Add AVRMCExprDylan McKay2016-09-264-0/+427
| | | | | | | | | | | | Summary: This adds the AVRMCExpr headers and implementation. Reviewers: arsenm, ruiu, grosbach, kparzysz Subscribers: wdng, beanz, mgorny, kparzysz, jtbandes, llvm-commits Differential Revision: https://reviews.llvm.org/D20503 llvm-svn: 282397
* Revert "[AMDGPU] Disassembler: print label names in branch instructions"Sam Kolton2016-09-263-156/+66
| | | | | | This reverts commit 6c6dbe625263ec9fcf8de0df27263cf147cde550. llvm-svn: 282396
* [AMDGPU] Disassembler: print label names in branch instructionsSam Kolton2016-09-263-66/+156
| | | | | | | | | | | | Summary: Add AMDGPUSymbolizer for finding names for labels from ELF symbol table. Reviewers: vpykhtin, artem.tamazov, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D24802 llvm-svn: 282394
* [ARM] Promote small global constants to constant poolsJames Molloy2016-09-268-6/+275
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a constant is unamed_addr and is only used within one function, we can save on the code size and runtime cost of an indirection by changing the global's storage to inside the constant pool. For example, instead of: ldr r0, .CPI0 bl printf bx lr .CPI0: &format_string format_string: .asciz "hello, world!\n" We can emit: adr r0, .CPI0 bl printf bx lr .CPI0: .asciz "hello, world!\n" This can cause significant code size savings when many small strings are used in one function (4 bytes per string). This recommit contains fixes for a nasty bug related to fast-isel fallback - because fast-isel doesn't know about this optimization, if it runs and emits references to a string that we inline (because fast-isel fell back to SDAG) we will end up with an inlined string and also an out-of-line string, and we won't emit the out-of-line string, causing backend failures. It also contains fixes for emitting .text relocations which made the sanitizer bots unhappy. llvm-svn: 282387
* [X86] Optimization for replacing LEA with MOV at frame index elimination timeZvi Rackover2016-09-261-1/+31
| | | | | | | | | | | | | | | Summary: Replace a LEA instruction of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx' MOV is preferable over LEA because usually there are more issue-slots available to execute MOVs than LEAs. Latest processors also support zero-latency MOVs. Fixes pr29022. Reviewers: hfinkel, delena, igorb, myatsina, mkuper Differential Revision: https://reviews.llvm.org/D24705 llvm-svn: 282385
* [X86][avx512] Fix bug in masked compress store.Ayman Musa2016-09-263-13/+28
| | | | | | Differential Revision: https://reviews.llvm.org/D23984 llvm-svn: 282381
* [X86] Remove what appears to be leftover MMX code involving (v1i64 ↵Craig Topper2016-09-251-4/+0
| | | | | | scalar_to_vector). llvm-svn: 282361
* [X86] Remove patterns for scalar_to_vector from FR32/FR64 to 256-bit ↵Craig Topper2016-09-251-4/+0
| | | | | | vectors. Lowering explicitly avoids creating this pattern. llvm-svn: 282360
* [AVX-512] Replace get512BitSuperRegister with calls to ↵Craig Topper2016-09-253-17/+10
| | | | | | TargetRegisterInfo::getMatchingSuperReg. llvm-svn: 282359
* [AVX-512] Fix some patterns predicates to properly enforce priority for ↵Craig Topper2016-09-251-4/+4
| | | | | | various versions of CVTDQ2PD instruction. llvm-svn: 282358
* [AVX-512] Add rounding versions of instructions to hasUndefRegUpdate.Craig Topper2016-09-251-0/+13
| | | | llvm-svn: 282357
* [AVX-512] Add the scalar unsigned integer to fp conversion instructions to ↵Craig Topper2016-09-251-0/+16
| | | | | | hasUndefRegUpdate. llvm-svn: 282356
* [AVX-512] Remove duplicate instructions for converting integer to scalar ↵Craig Topper2016-09-252-26/+22
| | | | | | floating point. We can use patterns to point to the other instructions instead. llvm-svn: 282355
* [AVX-512] Don't use two opcodes for INTR_TYPE_SCALAR_MASK_RM. The handling ↵Craig Topper2016-09-252-22/+21
| | | | | | was such that if the second opcode was present the first was ingored, so we can just have one opcode. llvm-svn: 282344
* [X86] Teach combineShuffle to avoid creating floating point operations with ↵Craig Topper2016-09-241-7/+12
| | | | | | | | integer types and integer operations with floating point types. Seems isOperationLegal lies for mismatched types and operations. Fixes PR30511. llvm-svn: 282341
* [AVX-512] Split scalar version of X86ISD::SELECT into a separate opcode ↵Craig Topper2016-09-243-4/+6
| | | | | | because isel is not robust with multiple type profiles for the same opcode. llvm-svn: 282340
* [AVX-512] Remove the patterns for selecting scalar VCOMI/VUCOMI instructions ↵Craig Topper2016-09-242-10/+6
| | | | | | with SAE as there is no way to create the pattern. llvm-svn: 282339
* [x86] don't try to create a vector integer inst for an SSE1 target (PR30512)Sanjay Patel2016-09-241-3/+4
| | | | | | | | | | | | This bug was introduced with: http://reviews.llvm.org/rL272511 We need to restrict the lowering to v4f32 comparisons because that's all SSE1 can handle. This should fix: https://llvm.org/bugs/show_bug.cgi?id=28044 llvm-svn: 282336
* [AVR] Update signature of AVRTargetObjectFile::SelectSectionForGlobalDylan McKay2016-09-242-3/+3
| | | | | | It was changed recently, and was breaking compilation of the backend. llvm-svn: 282329
* [RegisterBankInfo] Uniquely generate ValueMapping.Quentin Colombet2016-09-241-9/+9
| | | | | | | | This is a step toward statically allocate ValueMapping. Like the previous few commits, the goal is to move toward a TableGen'ed like structure with no dynamic allocation at all. llvm-svn: 282324
* [x86] fix FCOPYSIGN lowering to create constants instead of ConstantPool loadsSanjay Patel2016-09-231-43/+22
| | | | | | | | | | | | This is similar to: https://reviews.llvm.org/rL279958 By not prematurely lowering to loads, we should be able to more easily eliminate the 'or' with zero instructions seen in copysign-constant-magnitude.ll. We should also be able to extend this code to handle vectors. llvm-svn: 282312
* [AMDGPU] Fix for bz30427: wrong MTBUF encoding on VIValery Pykhtin2016-09-231-6/+10
| | | | | | Differential revision: https://reviews.llvm.org/D24875 llvm-svn: 282296
* Revert "[ARM] Promote small global constants to constant pools"James Molloy2016-09-238-275/+6
| | | | | | This reverts commit r282241. It caused http://lab.llvm.org:8011/builders/clang-native-arm-lnt/builds/19882. llvm-svn: 282249
* [Power9] Exploit move and splat instructions for build_vector improvementNemanja Ivanovic2016-09-235-5/+96
| | | | | | | | | | | | | | | This patch corresponds to review: https://reviews.llvm.org/D21135 This patch exploits the following instructions: mtvsrws lxvwsx mtvsrdd mfvsrld In order to improve some build_vector and extractelement patterns. llvm-svn: 282246
* [ARM] Promote small global constants to constant poolsJames Molloy2016-09-238-6/+275
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a constant is unamed_addr and is only used within one function, we can save on the code size and runtime cost of an indirection by changing the global's storage to inside the constant pool. For example, instead of: ldr r0, .CPI0 bl printf bx lr .CPI0: &format_string format_string: .asciz "hello, world!\n" We can emit: adr r0, .CPI0 bl printf bx lr .CPI0: .asciz "hello, world!\n" This can cause significant code size savings when many small strings are used in one function (4 bytes per string). This recommit contains fixes for a nasty bug related to fast-isel fallback - because fast-isel doesn't know about this optimization, if it runs and emits references to a string that we inline (because fast-isel fell back to SDAG) we will end up with an inlined string and also an out-of-line string, and we won't emit the out-of-line string, causing backend failures. It also contains fixes for emitting .text relocations which made the sanitizer bots unhappy. llvm-svn: 282241
* [AMDGPU] Refactor VOP1 and VOP2 instruction TD definitionsValery Pykhtin2016-09-2311-1691/+1379
| | | | | | Differential revision: https://reviews.llvm.org/D24738 llvm-svn: 282234
* [AVX-512] Split X86ISD::VFPROUND and X86ISD::VFPEXT into separate opcodes ↵Craig Topper2016-09-235-29/+24
| | | | | | | | for each type constraint. This revealed that scalar intrinsics could create nodes with a rounding mode of FROUND_CUR_DIRECTION, but the patterns didn't check for it. It just worked because isel doesn't check operand count and we had a pattern without the rounding mode argument at all. llvm-svn: 282231
* [AVX-512] Add separate ISD opcodes for each form of CVT instructions. Don't ↵Craig Topper2016-09-235-100/+104
| | | | | | reuse non-X86 ISD opcodes with extra X86 specific arguments. llvm-svn: 282230
* [AVX-512] Use different ISD opcodes for some of the scalar intrinsic ↵Craig Topper2016-09-234-27/+34
| | | | | | lowering. Isel is not very robust against using the same ISD opcode with different number of operands so its better to separate. llvm-svn: 282229
* AMDGPU/SI: Include implicit arguments in kernarg_segment_byte_sizeTom Stellard2016-09-233-1/+25
| | | | | | | | | | Reviewers: arsenm Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D24835 llvm-svn: 282223
* [AArch64][RegisterBankInfo] Sanity check TableGen'ed like inputs.Quentin Colombet2016-09-231-0/+47
| | | | | | | Make sure the entries written to mimic the behavior of TableGen are sane. llvm-svn: 282220
* [AArch64][RegisterBankInfo] Switch to TableGen'ed like PartialMapping.Quentin Colombet2016-09-232-20/+70
| | | | | | | | | Statically instanciate the most common PartialMappings. This should be closer to what the code would look like when TableGen support is added for GlobalISel. As a side effect, this should improve compile time. llvm-svn: 282215
* [RegisterBankInfo] Use array instead of SmallVector for BreakDown.Quentin Colombet2016-09-231-5/+12
| | | | | | | | | | | | | This is another step toward TableGen'ed like structures. The BreakDown of the mapping of the value will be statically computed by TableGen, thus we only have to point to the right entry in the table instead of dynamically allocate the mapping for each instruction. We still support the dynamic allocation through a factory of PartialMapping to ease the bring-up of the targets while the TableGen backend is not available. llvm-svn: 282213
* [RDF] Add initial support for lane masks in the DFGKrzysztof Parzyszek2016-09-225-62/+163
| | | | | | | Use lane masks for calculating covering and aliasing of register references. llvm-svn: 282194
* [Hexagon] Remove USR_OVF from CtrRegs register classKrzysztof Parzyszek2016-09-221-1/+4
| | | | | | | | | USR_OVF is a subregister of USR, which is a member of CtrRegs. Having both a register and its proper subregister in the same register class has bad consequences for lane mask calculation: based solely on the lane mask info, USR_OVF would not appear to be a subregister of USR. llvm-svn: 282192
* [RDF] Print the function name for calls in dumpsKrzysztof Parzyszek2016-09-221-3/+18
| | | | llvm-svn: 282191
* [RDF] Use uint32_t for register numbers instead of unsignedKrzysztof Parzyszek2016-09-222-8/+8
| | | | llvm-svn: 282190
* i386 does not support optimized swifterror handlingArnold Schwaighofer2016-09-222-3/+5
| | | | | | rdar://28432565 llvm-svn: 282186
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