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* Remove some unnecessary includes of PseudoSourceValue.h.Jay Foad2011-11-158-8/+0
| | | | llvm-svn: 144631
* Fix PR11370 for real. Prevents converting 256-bit FP instruction to AVX2 ↵Craig Topper2011-11-151-9/+17
| | | | | | 256-bit integer instructions when AVX2 isn't enabled. llvm-svn: 144629
* Properly qualify AVX2 specific parts of execution dependency table. Also ↵Craig Topper2011-11-152-9/+16
| | | | | | enable converting between 256-bit PS/PD operations when AVX1 is enabled. Fixes PR11370. llvm-svn: 144622
* Add vmov.f32 to materialize f32 immediate splats which cannot be handled byEvan Cheng2011-11-153-0/+28
| | | | | | integer variants. rdar://10437054 llvm-svn: 144608
* ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.Jim Grosbach2011-11-151-3/+66
| | | | | | rdar://10435076 llvm-svn: 144606
* Break false dependencies before partial register updates.Jakob Stoklund Olesen2011-11-152-0/+57
| | | | | | | | | | | | | | Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix about instructions with partial register updates causing false unwanted dependencies. The ExecutionDepsFix pass will break the false dependencies if the updated register was written in the previoius N instructions. The small loop added to sse-domains.ll runs twice as fast with dependency-breaking instructions inserted. llvm-svn: 144602
* ARM parsing datatype suffix variants for non-writeback VST1 instructions.Jim Grosbach2011-11-141-0/+44
| | | | | | rdar://10435076 llvm-svn: 144593
* ARM parsing datatype suffix variants for non-writeback VLD1 instructions.Jim Grosbach2011-11-141-0/+41
| | | | | | rdar://10435076 llvm-svn: 144592
* Add explanatory comment.Jim Grosbach2011-11-141-0/+1
| | | | llvm-svn: 144589
* Split out the plain '.{8|16|32|64}' suffix handling.Jim Grosbach2011-11-141-8/+24
| | | | | | | Make it easier to deal with aliases for instructions that do require a suffix but accept more specific variants of the same size. llvm-svn: 144588
* ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.Jim Grosbach2011-11-142-1/+38
| | | | | | rdar://10435076 llvm-svn: 144587
* Supporting inline memmove isn't going to be worthwhile. The only way to avoidChad Rosier2011-11-141-16/+9
| | | | | | | violating a dependency is to emit all loads prior to stores. This would likely cause a great deal of spillage offsetting any potential gains. llvm-svn: 144585
* ARM VLDR/VSTR instructions don't need a size suffix.Jim Grosbach2011-11-142-18/+11
| | | | | | | Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. llvm-svn: 144583
* Add support for inlining small memcpys.Chad Rosier2011-11-141-2/+63
| | | | | | rdar://10412592 llvm-svn: 144578
* Fix a performance regression from r144565. Positive offsets were being loweredChad Rosier2011-11-141-3/+3
| | | | | | into registers, rather then encoded directly in the load/store. llvm-svn: 144576
* ARM assembly parsing type suffix options for VLDR/VSTR.Jim Grosbach2011-11-142-0/+28
| | | | | | rdar://10435076 llvm-svn: 144575
* Add a missing pattern for X86ISD::MOVLPD. rdar://10436044Evan Cheng2011-11-141-0/+5
| | | | llvm-svn: 144566
* Add support for Thumb load/stores with negative offsets.Chad Rosier2011-11-141-16/+60
| | | | | | rdar://10412592 llvm-svn: 144565
* Unbreak Release builds.Benjamin Kramer2011-11-141-1/+1
| | | | llvm-svn: 144560
* Changed SSE4/AVX <2 x i64> extract and insert ops to be Custom loweredPete Cooper2011-11-141-5/+8
| | | | | | | | Constant idx case is still done in tablegen but other cases are then expanded Fixes <rdar://problem/10435460> llvm-svn: 144557
* 32-to-64-bit extended load.Akira Hatanaka2011-11-141-5/+10
| | | | llvm-svn: 144554
* AnalyzeCallOperands function for N32/64.Akira Hatanaka2011-11-142-0/+45
| | | | | | | | N32/64 places all variable arguments in integer registers (or on stack), regardless of their types, but follows calling convention of non-vaarg function when it handles fixed arguments. llvm-svn: 144553
* Modify LowerFormalArguments to correctly handle vaarg arguments for Mips64.Akira Hatanaka2011-11-141-14/+30
| | | | llvm-svn: 144552
* PTX: Let LLVM use loads/stores for all mem* intrinsics, instead of relying ↵Justin Holewinski2011-11-141-0/+5
| | | | | | on custom implementations. llvm-svn: 144551
* Remove variable that keeps the size of area used to save byval or variableAkira Hatanaka2011-11-143-12/+1
| | | | | | | | | | | argument registers on the callee's stack frame, along with functions that set and get it. It is not necessary to add the size of this area when computing stack size in emitPrologue, since it has already been accounted for in PEI::calculateFrameObjectOffsets. llvm-svn: 144549
* Tidy up. 80 column.Jim Grosbach2011-11-141-5/+8
| | | | llvm-svn: 144538
* Add AVX2 version of instructions to load folding tables. Also add a bunch of ↵Craig Topper2011-11-141-2/+139
| | | | | | missing SSE/AVX instructions. llvm-svn: 144525
* Add neverHasSideEffects, mayLoad, and mayStore to many patternless SSE/AVX ↵Craig Topper2011-11-142-19/+37
| | | | | | instructions. Remove MMX check from LowerVECTOR_SHUFFLE since MMX vector types won't go through it anyway. llvm-svn: 144522
* Add support for ARM halfword load/stores and signed byte loads with negativeChad Rosier2011-11-141-8/+15
| | | | | | | offsets. rdar://10412592 llvm-svn: 144518
* Add BLSI, BLSMSK, and BLSR to getTargetNodeName.Craig Topper2011-11-131-2/+6
| | | | llvm-svn: 144502
* The order in which the predicate is added differs between Thumb and ARM ↵Chad Rosier2011-11-131-10/+16
| | | | | | mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. llvm-svn: 144494
* Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing ↵Chad Rosier2011-11-131-0/+1
| | | | | | failures. llvm-svn: 144492
* Fix comments.Chad Rosier2011-11-131-3/+3
| | | | llvm-svn: 144490
* Add support for emitting both signed- and zero-extend loads. Fix Chad Rosier2011-11-131-32/+91
| | | | | | | | | | | | | SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8 offsets (addressing mode 3). This enables a load followed by an integer extend to be folded into a single load. For example: ldrb r1, [r0] ldrb r1, [r0] uxtb r2, r1 => mov r3, r2 mov r3, r1 llvm-svn: 144488
* Add more AVX2 shift lowering support. Move AVX2 variable shift to use ↵Craig Topper2011-11-122-62/+153
| | | | | | patterns instead of custom lowering code. llvm-svn: 144457
* Fix typo.Akira Hatanaka2011-11-121-1/+1
| | | | llvm-svn: 144453
* Implement Mips64's handling of byval arguments in LowerCall.Akira Hatanaka2011-11-121-12/+100
| | | | llvm-svn: 144452
* Implement Mips64's handling of byval arguments in LowerFormalArguments.Akira Hatanaka2011-11-121-18/+60
| | | | llvm-svn: 144449
* 64-bit arbitrary immediate pattern.Akira Hatanaka2011-11-121-0/+4
| | | | llvm-svn: 144448
* Function for handling byval arguments.Akira Hatanaka2011-11-122-4/+43
| | | | llvm-svn: 144447
* build: Attempt to rectify inconsistencies between CMake and LLVMBuild ↵Daniel Dunbar2011-11-1225-21/+25
| | | | | | | | versions of explicit dependencies. - The hope is that we have a tool/test to verify these are accurate (and tight) soon. llvm-svn: 144444
* ARM refactor simple immediate asm operand render methods.Jim Grosbach2011-11-124-79/+22
| | | | | | | These immediate operands all use the same simple logic for rendering to MCInst, so have them share the method for doing so. llvm-svn: 144439
* Re-apply 144430, this time with the associated isel and disassmbler bits.Jim Grosbach2011-11-123-11/+6
| | | | | | Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.' llvm-svn: 144437
* Oops. Missed the isel half of this. revert while I sort that out.Jim Grosbach2011-11-111-3/+4
| | | | llvm-svn: 144431
* ARM assembly parsing for VST1 two-register encoding.Jim Grosbach2011-11-111-4/+3
| | | | llvm-svn: 144430
* ARM optional size suffix for VLDR/VSTR syntax.Jim Grosbach2011-11-111-0/+9
| | | | llvm-svn: 144427
* Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.Chad Rosier2011-11-111-10/+60
| | | | llvm-svn: 144426
* CMake: Fix CMake build for new Mips tblgen file.Daniel Dunbar2011-11-111-0/+1
| | | | llvm-svn: 144423
* ARM vldm and vstm VFP instructions can take a data type suffix.Jim Grosbach2011-11-111-0/+22
| | | | | | | | | | | | It's ignored by the assembler when present, but is legal syntax. Other instructions have something similar, but for some mnemonics it's only sometimes not significant, so this quick check in the parser will need refactored into something more robust soon-ish. This gets some basics working in the meantime. Partial for rdar://10435264 llvm-svn: 144422
* Target/LLVMBuild: Order components alphabetically.Daniel Dunbar2011-11-111-16/+16
| | | | llvm-svn: 144415
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