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* Add MCSubtargetInfo target registry stuff.Evan Cheng2011-07-011-0/+28
| | | | llvm-svn: 134279
* Calling-convention specifications for illegal types are no-ops. Simplify ↵Eli Friedman2011-07-011-30/+11
| | | | | | based on this. llvm-svn: 134264
* ARMv7M vs. ARMv7E-M support.Jim Grosbach2011-07-016-49/+114
| | | | | | | | | | | | | | The DSP instructions in the Thumb2 instruction set are an optional extension in the Cortex-M* archtitecture. When present, the implementation is considered an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation." Add a subtarget feature hook for the v7e-m instructions and hook it up. The cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is a v7e-m implementation. rdar://9572992 llvm-svn: 134261
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-0128-56/+56
| | | | llvm-svn: 134259
* - Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng2011-07-0126-28/+156
| | | | | | | | | itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. llvm-svn: 134257
* Fix off-by-one error.Jim Grosbach2011-07-011-1/+1
| | | | | | (low two bits always zero, so off by one bit of encoded value). llvm-svn: 134247
* Hide the call to InitMCInstrInfo into tblgen generated ctor.Evan Cheng2011-07-0127-51/+85
| | | | llvm-svn: 134244
* Pseudo-ize t2MOVCC[ri].Jim Grosbach2011-07-014-55/+18
| | | | | | | | t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them. The Thumb1 versions, tMOVCC[ri] were only present for use by the size- reduction pass, so they're no longer necessary at all and can be deleted. llvm-svn: 134242
* Improve Mips back-end's handling of DBG_VALUE. Akira Hatanaka2011-07-015-23/+70
| | | | llvm-svn: 134224
* Add support for the 'j' immediate constraint. This is conditionalized onEric Christopher2011-07-011-0/+9
| | | | | | | | supporting the instruction that the constraint is for 'movw'. Part of rdar://9119939 llvm-svn: 134222
* Add support for the ARM 't' register constraint. And another testcaseEric Christopher2011-07-011-0/+5
| | | | | | | | for the 'x' register constraint. Part of rdar://9119939 llvm-svn: 134220
* We'll return a null RC by default if we can't match.Eric Christopher2011-07-011-2/+1
| | | | | | Part of rdar://9119939 llvm-svn: 134217
* Add support for the 'x' constraint.Eric Christopher2011-07-011-0/+9
| | | | | | Part of rdar://9307836 and rdar://9119939 llvm-svn: 134215
* Capitalize the unsigned part of the initializer.Eric Christopher2011-06-301-1/+1
| | | | llvm-svn: 134211
* Rename Pair to RCPair lacking any better naming ideas.Eric Christopher2011-06-301-10/+10
| | | | llvm-svn: 134210
* Use the correct registers on X86_64.Bill Wendling2011-06-301-4/+4
| | | | llvm-svn: 134208
* Fix a problem with fast-isel return values introduced in r134018.Jakob Stoklund Olesen2011-06-301-2/+3
| | | | | | | | | We would put the return value from long double functions in the wrong register. This fixes gcc.c-torture/execute/conversion.c llvm-svn: 134205
* Refact ARM Thumb1 tMOVr instruction family.Jim Grosbach2011-06-309-86/+26
| | | | | | | | | | Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions into tMOVr. There's no need to keep them separate. Giving the tMOVr instruction the proper GPR register class for its operands is sufficient to give the register allocator enough information to do the right thing directly. llvm-svn: 134204
* Add support for the 'h' constraint.Eric Christopher2011-06-302-1/+10
| | | | | | Part of rdar://9119939 llvm-svn: 134203
* Add target a target hook to get the register number used by the compact unwindBill Wendling2011-06-302-0/+19
| | | | | | | encoding for the registers it knows about. Return -1 if it can't handle that register. llvm-svn: 134202
* Add a convenience typedef for std::pair<unsigned, const TargetRegisterClass*>.Eric Christopher2011-06-301-7/+8
| | | | | | | | No functional change. Part of rdar://9119939 llvm-svn: 134198
* Thumb1 register to register MOV instruction is predicable.Jim Grosbach2011-06-308-51/+60
| | | | | | | | | Fix a FIXME and allow predication (in Thumb2) for the T1 register to register MOV instructions. This allows some better codegen with if-conversion (as seen in the test updates), plus it lays the groundwork for pseudo-izing the tMOVCC instructions. llvm-svn: 134197
* Tweak error messages to match GCC. Should fix gcc.target/i386/pr30848.cJakob Stoklund Olesen2011-06-301-3/+3
| | | | llvm-svn: 134193
* Pseudo-ize the Thumb tTPsoft instruction.Jim Grosbach2011-06-303-24/+7
| | | | | | | It's just a call to a special helper function. Get rid of the T2 variant entirely, as it's identical to the Thumb1 version. llvm-svn: 134178
* Pseudo-ize the t2LDMIA_RET instruction.Jim Grosbach2011-06-302-19/+12
| | | | | | | | It's just a t2LDMIA_UPD instruction with extra codegen properties, so it doesn't need the encoding information. As a side-benefit, we now correctly recognize for instruction printing as a 'pop' instruction. llvm-svn: 134173
* Pseudo-ize the Thumb tPOP_RET instruction.Jim Grosbach2011-06-302-9/+10
| | | | | | | It's just a tPOP instruction with additional code-gen properties, so it doesn't need encoding information. llvm-svn: 134172
* Kill dead code.Jim Grosbach2011-06-301-1/+0
| | | | llvm-svn: 134131
* Size reducing SP adjusting t2ADDri needs to check predication.Jim Grosbach2011-06-301-1/+4
| | | | | | | tADDrSPi is not predicable, so we can't size-reduce a t2ADDri to it if the predicate is anything other than "always." llvm-svn: 134130
* Fix ARMSubtarget feature parsing.Evan Cheng2011-06-301-10/+7
| | | | llvm-svn: 134129
* Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-3056-145/+210
| | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! llvm-svn: 134127
* Recognize the xstorerng alias for VIA PadLock's xstore instruction.Joerg Sonnenberger2011-06-301-0/+2
| | | | llvm-svn: 134126
* Make sure we use the correct register class here since we'll need toEric Christopher2011-06-301-1/+2
| | | | | | care about spill values. llvm-svn: 134122
* Fix a small thinko for constant i64 lock/orq optimization where weEric Christopher2011-06-301-2/+4
| | | | | | | | we didn't have an opcode for 64-bit constant or expressions. Fixes rdar://9692967 llvm-svn: 134121
* Remove redundant Thumb2 ADD/SUB SP instruction definitions.Jim Grosbach2011-06-296-113/+55
| | | | | | | | | | Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the stack pointer. It can just use the normal add-register-immediate encoding since it can use all registers as a source, not just R0-R7. The extra instruction definitions are just duplicates of the normal instructions with the (not well enforced) constraint that the source register was SP. llvm-svn: 134114
* Always adjust the stack pointer immediately after the call.Jakob Stoklund Olesen2011-06-291-0/+7
| | | | | | | | | | | | | | | | | | | Some x86-32 calls pop values off the stack, and we need to readjust the stack pointer after the call. This happens when ADJCALLSTACKUP is eliminated. It could happen that spill code was inserted between the CALL and ADJCALLSTACKUP instructions, and we would compute wrong stack pointer offsets for those frame index references. Fix this by inserting the stack pointer adjustment immediately after the call instead of where the ADJCALLSTACKUP instruction was erased. I don't have a test case since we don't currently insert code in that position. We will soon, though. I am testing a regalloc patch that didn't work on Linux because of this. llvm-svn: 134113
* In the ARM global merging pass, allow extraneous alignment specifiers. This passCameron Zwarich2011-06-291-2/+4
| | | | | | | | already makes the assumption, which is correct on ARM, that a type's alignment is less than its alloc size. This improves codegen with Clang (which inserts a lot of extraneous alignment specifiers) and fixes <rdar://problem/9695089>. llvm-svn: 134106
* Remove getRegClassForInlineAsmConstraint from the ARM port.Eric Christopher2011-06-292-59/+15
| | | | | | Part of rdar://9643582 llvm-svn: 134095
* Remove todo.Eric Christopher2011-06-291-2/+0
| | | | llvm-svn: 134094
* Refactor away tSpill and tRestore pseudos in ARM backend.Jim Grosbach2011-06-295-36/+8
| | | | | | | The tSpill and tRestore instructions are just copies of the tSTRspi and tLDRspi instructions, respectively. Just use those directly instead. llvm-svn: 134092
* Add a TODO for the Alpha port inline asm constraints.Eric Christopher2011-06-291-0/+2
| | | | llvm-svn: 134089
* Move Alpha from getRegClassForInlineAsmConstraint toEric Christopher2011-06-292-32/+14
| | | | | | | | getRegForInlineAsmConstraint. Part of rdar://9643582 llvm-svn: 134088
* Update comment for getRegForInlineAsmConstraint for Mips.Eric Christopher2011-06-291-3/+3
| | | | llvm-svn: 134087
* Move the Blackfin port away from getRegClassForInlineAsmConstraint byEric Christopher2011-06-293-29/+22
| | | | | | | | creating a few specific register classes. Part of rdar://9643582 llvm-svn: 134086
* Remove getRegClassForInlineAsmConstraint from MBlaze. Add a TODO commentEric Christopher2011-06-292-33/+7
| | | | | | | | for the port. Part of rdar://9643582 llvm-svn: 134085
* Remove getRegClassForInlineAsmConstraint for Mips.Eric Christopher2011-06-292-48/+3
| | | | | | Part of rdar://9643582 llvm-svn: 134084
* Remove getRegClassForInlineAsmConstraint from sparc.Eric Christopher2011-06-292-24/+0
| | | | | | Part of rdar://9643582 llvm-svn: 134083
* Move XCore from getRegClassForInlineAsmConstraint toEric Christopher2011-06-292-17/+14
| | | | | | | | getRegForInlineAsmConstraint. Part of rdar://9643582 llvm-svn: 134080
* Use getRegForInlineAsmConstraint instead of custom defining regclassesEric Christopher2011-06-292-56/+24
| | | | | | | | via vectors. Part of rdar://9643582 llvm-svn: 134079
* Fix CMake build.NAKAMURA Takumi2011-06-291-1/+0
| | | | llvm-svn: 134055
* Sink SubtargetFeature and TargetInstrItineraries (renamed ↵Evan Cheng2011-06-298-398/+8
| | | | | | MCInstrItineraries) into MC. llvm-svn: 134049
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