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* Fix indent in comment.Nick Lewycky2011-10-121-1/+1
| | | | llvm-svn: 141749
* Fix -widen-vmovs liveness issues.Jakob Stoklund Olesen2011-10-121-3/+29
| | | | | | | | | | | | | | | | | | | | | | When widening a copy, we are reading a larger register that may not be live. Use an <undef> flag to tell the register scavenger and machine code verifier that we know the value isn't defined. We now widen: %S6<def> = COPY %S4<kill>, %D3<imp-def> into: %D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill> This also keeps the <kill> flag on %S4 so we don't inadvertently kill a live value in %S5. Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves the <undef> flag when converting VMOVD to VORR. llvm-svn: 141746
* Change name of class to ArithOverflowR.Akira Hatanaka2011-10-111-3/+3
| | | | llvm-svn: 141743
* Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logicalAkira Hatanaka2011-10-112-35/+19
| | | | | | instructions with two register operands derive from it. llvm-svn: 141742
* Fix comment.Akira Hatanaka2011-10-111-1/+1
| | | | llvm-svn: 141737
* Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bitAkira Hatanaka2011-10-112-43/+25
| | | | | | | arithmetic and logical instructions with three register operands derive from them. Fix instruction encoding too. llvm-svn: 141736
* Fix function isUnalignedLoadStore.Akira Hatanaka2011-10-111-2/+4
| | | | llvm-svn: 141722
* ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.Jim Grosbach2011-10-112-64/+139
| | | | | | | | Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
* Remove unused PatLeaf.Akira Hatanaka2011-10-111-4/+0
| | | | llvm-svn: 141720
* Change the names of 64-bit logical instructions so that they match the names ofAkira Hatanaka2011-10-111-8/+8
| | | | | | the real instructions. llvm-svn: 141718
* Revert r141529. This is causing failures in the test-suite, like bigstack ↵Bill Wendling2011-10-111-11/+2
| | | | | | and ReedSolomon. Boo... llvm-svn: 141716
* Remove redundancy in setcc patterns using multiclass.Akira Hatanaka2011-10-112-48/+47
| | | | llvm-svn: 141715
* Use sltiu instead of sltu when a register operand and immediate are compared.Akira Hatanaka2011-10-112-2/+2
| | | | llvm-svn: 141708
* ARM addressing mode cleanup for LDC/STC.Jim Grosbach2011-10-111-16/+20
| | | | | | | We parse at least some forms of the instructions now. Encoding is pretty screwed up, still, though. llvm-svn: 141704
* Add patterns for conditional branches with 64-bit register operands.Akira Hatanaka2011-10-112-21/+30
| | | | llvm-svn: 141696
* Add support for 64-bit set-on-less-than instructions.Akira Hatanaka2011-10-112-14/+44
| | | | llvm-svn: 141695
* Add support for conditional branch instructions with 64-bit register operands.Akira Hatanaka2011-10-114-34/+67
| | | | llvm-svn: 141694
* ARM parse alignment specifier for NEON load/store instructions.Jim Grosbach2011-10-112-29/+93
| | | | llvm-svn: 141682
* ARM Rename operand sub-structure 'Mem' to 'Memory' for a bit more clarity.Jim Grosbach2011-10-111-113/+113
| | | | llvm-svn: 141671
* Implement the emitFrameIndexDebugValue and getDebugValueLocation hooks.Richard Osborne2011-10-113-6/+64
| | | | | | | This fixes an assert due to the operands of the DBG_VALUE instruction not being as expected (PR11105). llvm-svn: 141666
* Fix a iterator out of bounds error, that triggers rarely.Kalle Raiskila2011-10-111-0/+2
| | | | llvm-svn: 141665
* Add HasPOPCNT predicate to the POPCNT instructions. Also mark POPCNT as ↵Craig Topper2011-10-112-20/+23
| | | | | | modifying EFLAGS. llvm-svn: 141656
* Make Ivy Bridge 16-bit floating point conversion instructions require AVX.Craig Topper2011-10-111-1/+1
| | | | llvm-svn: 141654
* Add X86 LZCNT instruction. Including instruction selection support.Craig Topper2011-10-115-7/+50
| | | | llvm-svn: 141651
* Fix disassembling of popcntw. Also remove some code that says it accounts ↵Craig Topper2011-10-112-68/+3
| | | | | | for 64BIT_REXW_XD not existing, but it does exist. llvm-svn: 141642
* Make changes necessary for supporting floating point load and store instructionsAkira Hatanaka2011-10-114-23/+50
| | | | | | | that have 64-bit pointers or access the 32 x 64-bit floating pointer register file. Update functions in MipsInstrInfo.cpp too. llvm-svn: 141623
* Move -widen-vmovs to ARMBaseInstrInfo::expandPostRAPseudo().Jakob Stoklund Olesen2011-10-112-30/+44
| | | | | | | | | | | The VMOVS widening needs to look at the implicit COPY operands. Trying to dig out the COPY instruction from an iterator in copyPhysReg() is the wrong approach. The expandPostRAPseudo() hook gets to look at COPY instructions before they are converted to copyPhysReg() calls. llvm-svn: 141619
* Modify lowering of GlobalAddress so that correct code is emitted when target isAkira Hatanaka2011-10-113-14/+23
| | | | | | Mips64. llvm-svn: 141618
* Fixed natural stack alignment for Linux x86-32. Thanks Eli.Lang Hames2011-10-111-1/+1
| | | | llvm-svn: 141616
* Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too.Akira Hatanaka2011-10-111-7/+10
| | | | llvm-svn: 141615
* Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot.Akira Hatanaka2011-10-112-17/+24
| | | | llvm-svn: 141613
* Add definitions of 64-bit loads and stores. Add a patterns for unalignedAkira Hatanaka2011-10-113-1/+38
| | | | | | zextloadi32 for which there is no corresponding pseudo or real instruction. llvm-svn: 141608
* Change definitions of classes LoadM and StoreM in preparation for adding supportAkira Hatanaka2011-10-112-20/+65
| | | | | | | for 64-bit load and store instructions. Add definitions of 64-bit memory operand and 16-bit immediate operand. llvm-svn: 141603
* Simplify check that optional def is there and is CPSR.Bill Wendling2011-10-111-5/+4
| | | | llvm-svn: 141602
* Add a natural stack alignment field to TargetData, and prevent InstCombine fromLang Hames2011-10-105-12/+27
| | | | | | | | | | | | | | promoting allocas to preferred alignments that exceed the natural alignment. This avoids some potentially expensive dynamic stack realignments. The natural stack alignment is set in target data strings via the "S<size>" option. Size is in bits and must be a multiple of 8. The natural stack alignment defaults to "unspecified" (represented by a zero value), and the "unspecified" value does not prevent any alignment promotions. Target maintainers that care about avoiding promotions should explicitly add the "S<size>" option to their target data strings. llvm-svn: 141599
* Simplify operand Kind checks a bit.Jim Grosbach2011-10-101-20/+20
| | | | llvm-svn: 141592
* Reapply r141365 now that PR11107 is fixed.Bill Wendling2011-10-104-0/+165
| | | | llvm-svn: 141591
* Add a name to sub-operand for clarity.Jim Grosbach2011-10-101-1/+1
| | | | llvm-svn: 141590
* If the CPSR is defined by a copy, then we don't want to merge it into an ITBill Wendling2011-10-101-0/+22
| | | | | | | | | | | | | | | | | | | | | block. E.g., if we have: movs r1, r1 rsb r1, 0 movs r2, r2 rsb r2, 0 we don't want this to be converted to: movs r1, r1 movs r2, r2 itt mi rsb r1, 0 rsb r2, 0 PR11107 & <rdar://problem/10259534> llvm-svn: 141589
* Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. ↵Eli Friedman2011-10-101-12/+4
| | | | | | Fixes PR11102. llvm-svn: 141585
* X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy ↵Benjamin Kramer2011-10-101-0/+5
| | | | | | bridge. llvm-svn: 141571
* Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because theNadav Rotem2011-10-101-11/+3
| | | | | | instruction set has no 64-bit SRA support. llvm-svn: 141570
* X86: Add patterns for the movbe instruction (mov + bswap, only available on ↵Benjamin Kramer2011-10-103-12/+13
| | | | | | atom) llvm-svn: 141563
* Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame toBill Wendling2011-10-104-165/+0
| | | | | | hang, and possibly SPEC/CINT2006/464_h264ref. llvm-svn: 141560
* When getting the number of bits necessary for addressing modeBill Wendling2011-10-101-2/+11
| | | | | | | | ARMII::AddrModeT1_s, we need to take into account that if the frame register is ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of bits is 5. llvm-svn: 141529
* Put a bunch of calls to ToggleFeature behind proper if statements.Craig Topper2011-10-101-17/+42
| | | | llvm-svn: 141527
* Fix a regression from r138445. If we're loading from the frame/base pointerChad Rosier2011-10-101-0/+1
| | | | | | | | the tADDrSPi instruction can't be used. Make sure we're updating the opcode to tADDi3 in all cases. rdar://10254707 llvm-svn: 141523
* PTX: Print .ptr kernel attributes if PTX version >= 2.2Justin Holewinski2011-10-094-1/+49
| | | | llvm-svn: 141508
* Add Ivy Bridge 16-bit floating point conversion instructions for the X86 ↵Craig Topper2011-10-095-3/+42
| | | | | | disassembler. llvm-svn: 141505
* Prevent potential NOREX bug.Jakob Stoklund Olesen2011-10-081-0/+11
| | | | | | | | | | | | | | | A GR8_NOREX virtual register is created when extrating a sub_8bit_hi sub-register: %vreg2<def> = COPY %vreg1:sub_8bit_hi; GR8_NOREX:%vreg2 %GR64_ABCD:%vreg1 TEST8ri_NOREX %vreg2, 1, %EFLAGS<imp-def>; GR8_NOREX:%vreg2 If such a live range is ever split, its register class must not be inflated to GR8. The sub-register copy can only target GR8_NOREX. I dont have a test case for this theoretical bug. llvm-svn: 141500
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