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* ARM: Tidy up. Remove unused template parameters.Jim Grosbach2012-08-021-20/+16
| | | | llvm-svn: 161222
* ARM: More InstAlias refactors to use #NAME#.Jim Grosbach2012-08-021-42/+27
| | | | llvm-svn: 161220
* ARM: Refactor instaliases using TableGen support for #NAME#.Jim Grosbach2012-08-021-31/+23
| | | | | | | | Now that TableGen supports references to NAME w/o it being explicitly referenced in the definition's own name, use that to simplify assembly InstAlias definitions in multiclasses. llvm-svn: 161218
* X86 Peephole: fold loads to the source register operand if possible.Manman Ren2012-08-021-1/+5
| | | | | | | | | | Add more comments and use early returns to reduce nesting in isLoadFoldable. Also disable folding for V_SET0 to avoid introducing a const pool entry and a const pool load. rdar://10554090 and rdar://11873276 llvm-svn: 161207
* Move the code that creates instances of MipsInstrInfo and MipsFrameLowering outAkira Hatanaka2012-08-029-29/+51
| | | | | | of MipsTargetMachine.cpp. llvm-svn: 161191
* Set transient stack alignment in constructor of MipsFrameLowering and re-enableAkira Hatanaka2012-08-021-3/+2
| | | | | | test o32_cc_vararg.ll. llvm-svn: 161189
* Support fpv4 for ARM Cortex-M4.Jiangning Liu2012-08-021-1/+1
| | | | llvm-svn: 161163
* Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ↵Jiangning Liu2012-08-023-16/+29
| | | | | | index issue. llvm-svn: 161162
* Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.Jiangning Liu2012-08-023-40/+75
| | | | llvm-svn: 161161
* Fix #13241, a bug around shift immediate operand for ARM instruction ADR.Jiangning Liu2012-08-026-7/+64
| | | | llvm-svn: 161159
* X86 Peephole: fold loads to the source register operand if possible.Manman Ren2012-08-022-0/+83
| | | | | | | | | | | | Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. This patch is a rework of r160919 and was tested on clang self-host on my local machine. rdar://10554090 and rdar://11873276 llvm-svn: 161152
* X86: mark GATHER instructios as mayLoadManman Ren2012-08-011-1/+1
| | | | llvm-svn: 161143
* ARM: Remove redundant instalias.Jim Grosbach2012-08-011-3/+0
| | | | llvm-svn: 161134
* Clean up formatting.Jim Grosbach2012-08-012-13/+2
| | | | llvm-svn: 161133
* Tidy up.Jim Grosbach2012-08-011-11/+4
| | | | llvm-svn: 161132
* Whitespace.Chad Rosier2012-08-0117-135/+134
| | | | llvm-svn: 161122
* Added FMA functionality to X86 target.Elena Demikhovsky2012-08-015-117/+277
| | | | llvm-svn: 161110
* Add more indirection to the disassembler tables to reduce amount of space ↵Craig Topper2012-08-015-14/+18
| | | | | | used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data. llvm-svn: 161101
* Implement MipsJITInfo::replaceMachineCodeForFunction.Akira Hatanaka2012-08-011-1/+46
| | | | | | | | | | No new test case is added. This patch makes test JITTest.FunctionIsRecompiledAndRelinked pass on mips platform. Patch by Petar Jovanovic. llvm-svn: 161098
* Remove unused variable.Akira Hatanaka2012-08-011-1/+0
| | | | llvm-svn: 161095
* Implement MipsSERegisterInfo::eliminateCallFramePseudoInstr. The function emitsAkira Hatanaka2012-07-319-41/+71
| | | | | | | instructions that decrement and increment the stack pointer before and after a call when the function does not have a reserved call frame. llvm-svn: 161093
* Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo andAkira Hatanaka2012-07-3113-72/+268
| | | | | | MipsSERegisterInfo. llvm-svn: 161092
* Add definitions of two subclasses of MipsFrameLowering, Mips16FrameLowering andAkira Hatanaka2012-07-319-219/+415
| | | | | | | | | | MipsSEFrameLowering. Implement MipsSEFrameLowering::hasReservedCallFrame. Call frames will not be reserved if there is a call with a large call frame or there are variable sized objects on the stack. llvm-svn: 161090
* Add Mips16InstrInfo.cpp and MipsSEInstrInfo.cpp to CMakeLists.txt.Akira Hatanaka2012-07-311-0/+2
| | | | llvm-svn: 161083
* Add definitions of two subclasses of MipsInstrInfo, MipsInstrInfo (for mips16),Akira Hatanaka2012-07-319-361/+624
| | | | | | and MipsSEInstrInfo (for mips32/64). llvm-svn: 161081
* Delete mips64 target machine classes. mips target machines can be used in placeAkira Hatanaka2012-07-312-88/+46
| | | | | | of them. llvm-svn: 161080
* Let PEI::calculateFrameObjectOffsets compute the final stack size rather thanAkira Hatanaka2012-07-312-12/+1
| | | | | | computing it in MipsFrameLowering::emitPrologue. llvm-svn: 161078
* Expand DYNAMIC_STACKALLOC nodes rather than doing custom-lowering.Akira Hatanaka2012-07-314-66/+6
| | | | | | | The frame object which points to the dynamically allocated area will not be needed after changes are made to cease reserving call frames. llvm-svn: 161076
* Define ADJCALLSTACKDOWN/UP nodes. These nodes are emitted regardless of whetherAkira Hatanaka2012-07-314-38/+33
| | | | | | | or not it is in mips16 mode. Define MipsPseudo (mode-independant pseudo) and PseudoSE (mips32/64 pseudo) classes. llvm-svn: 161071
* Change name of class MipsInst to InstSE to distinguish it from mips16'sAkira Hatanaka2012-07-312-16/+16
| | | | | | instruction class. SE stands for standard encoding. llvm-svn: 161069
* When store nodes or memcpy nodes are created to copy the function callAkira Hatanaka2012-07-312-48/+32
| | | | | | | arguments to the stack in MipsISelLowering::LowerCall, use stack pointer and integer offset operands rather than frame object operands. llvm-svn: 161068
* [x86 frame lowering] In 32-bit mode, use ESI as the base pointer.Chad Rosier2012-07-311-2/+4
| | | | | | | Previously, we were using EBX, but PIC requires the GOT to be in EBX before function calls via PLT GOT pointer. llvm-svn: 161066
* Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined asAkira Hatanaka2012-07-313-38/+17
| | | | | | | | | single-precision load and store. Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect to map unaligned floating point load/store nodes to these instructions. llvm-svn: 161063
* Make INSTRUCTION_SPECIFIER_FIELDS match X86DisassemblerCommon.h. Also remove ↵Craig Topper2012-07-311-5/+4
| | | | | | trailing whitespace. llvm-svn: 161029
* Tidy up trailing whitespaceCraig Topper2012-07-311-33/+33
| | | | llvm-svn: 161027
* Tidy up trailing whitespaceCraig Topper2012-07-311-12/+12
| | | | llvm-svn: 161026
* Fix a bug in ARMMachObjectWriter::RecordRelocation() in ARMMachObjectWriter.cppKevin Enderby2012-07-301-2/+9
| | | | | | | | | where the other_half of the movt and movw relocation entries needs to get set and only with the 16 bits of the other half. rdar://10038370 llvm-svn: 160978
* Mark MOVZX16/MOVSX16 as neverHasSideEffects/mayLoadCraig Topper2012-07-301-0/+6
| | | | llvm-svn: 160953
* Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The ↵Craig Topper2012-07-301-0/+2
| | | | | | isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code. llvm-svn: 160951
* Give VCVTTPD2DQ priority over CVTTPD2DQ.Craig Topper2012-07-301-10/+10
| | | | llvm-svn: 160942
* Fix patterns for CVTTPS2DQ to specify SSE2 instead of SSE1.Craig Topper2012-07-303-43/+46
| | | | llvm-svn: 160941
* Fix up patterns for VCVTSS2SD. Specifically give it priority over SSE form. ↵Craig Topper2012-07-301-9/+10
| | | | | | Add an OptForSpeed to explicitly pair up with an OptForSize that was already on another pattern. llvm-svn: 160939
* Fix load types on intrinsic forms of SS2SD and SD2SS AVX/SSE convert ↵Craig Topper2012-07-291-26/+41
| | | | | | instruction patterns. llvm-svn: 160938
* Move more SSE/AVX convert instruction patterns into their definitions.Craig Topper2012-07-291-70/+50
| | | | llvm-svn: 160937
* Revert r160920 and r160919 due to dragonegg and clang selfhost failureManman Ren2012-07-292-77/+0
| | | | llvm-svn: 160927
* Fold patterns for some of the SSE/AVX convert instructions into their ↵Craig Topper2012-07-281-49/+34
| | | | | | instruction definitions. llvm-svn: 160922
* Mark some of the SSE/AVX convert instructions as mayLoad/neverHasSideEffects.Craig Topper2012-07-281-22/+23
| | | | llvm-svn: 160921
* X86 Peephole: fold loads to the source register operand if possible.Manman Ren2012-07-282-0/+77
| | | | | | | | | Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. rdar://10554090 and rdar://11873276 llvm-svn: 160919
* Make CVTSS2SI instruction definition consistent with CVTSD2SI.Craig Topper2012-07-281-34/+14
| | | | llvm-svn: 160914
* Fix up memory load types for SSE scalar convert intrinsic patterns.Craig Topper2012-07-281-27/+26
| | | | llvm-svn: 160913
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