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* Fix disassembling of VCVTSD2SICraig Topper2011-08-261-10/+4
| | | | llvm-svn: 138623
* Atomic load/store on ARM/Thumb.Eli Friedman2011-08-263-0/+63
| | | | | | | | | | | | I don't really like the patterns, but I'm having trouble coming up with a better way to handle them. I plan on making other targets use the same legalization ARM-without-memory-barriers is using... it's not especially efficient, but if anyone cares, it's not that hard to fix for a given target if there's some better lowering. llvm-svn: 138621
* Do the same as r138461. Mark VZEROALL as clobbering all YMM registersBruno Cardoso Lopes2011-08-251-4/+3
| | | | llvm-svn: 138592
* Remove stray fullstop.Nick Lewycky2011-08-251-1/+1
| | | | llvm-svn: 138589
* Add support for AVX 256-bit version of MOVDDUP!Bruno Cardoso Lopes2011-08-252-0/+47
| | | | llvm-svn: 138588
* Make isMOVDDUP mask check more strict and update comments!Bruno Cardoso Lopes2011-08-251-2/+7
| | | | llvm-svn: 138587
* Port over additional encoding tests to decoding tests, and fix an operand ↵Owen Anderson2011-08-251-1/+1
| | | | | | ordering bug this exposed. llvm-svn: 138575
* ARM fix for missing implicit operands on ldmia_ret.Andrew Trick2011-08-251-1/+3
| | | | | | rdar://10005094: miscompile of 176.gcc llvm-svn: 138568
* whitespaceAndrew Trick2011-08-251-1/+1
| | | | llvm-svn: 138566
* Explicitly disallow predication in Thumb1 assembly.Jim Grosbach2011-08-251-0/+6
| | | | llvm-svn: 138562
* Add more missing TB encodings to VEX instructions to allow them to be ↵Craig Topper2011-08-251-36/+36
| | | | | | disassembled. Fixes remainder of PR10678. llvm-svn: 138553
* Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be ↵Craig Topper2011-08-251-8/+8
| | | | | | disassembled. Fixes PR10723. llvm-svn: 138551
* Add support for 256-bit versions of VSHUFPD and VSHUFPS.Bruno Cardoso Lopes2011-08-252-18/+204
| | | | llvm-svn: 138546
* Add memory version of SHUFPD to mask decoding!Bruno Cardoso Lopes2011-08-251-1/+3
| | | | llvm-svn: 138545
* Hide -global-merge option.Evan Cheng2011-08-251-1/+1
| | | | llvm-svn: 138540
* Add a command line option to disable global merge pass.Evan Cheng2011-08-251-1/+6
| | | | llvm-svn: 138536
* Remove a out-of-place comment.Evan Cheng2011-08-251-1/+0
| | | | llvm-svn: 138534
* Create a section for non-instructions patterns in the beginning of theBruno Cardoso Lopes2011-08-241-88/+82
| | | | | | file, and move more code around! llvm-svn: 138521
* Move code around!Bruno Cardoso Lopes2011-08-241-58/+66
| | | | llvm-svn: 138520
* Organize UNPCK* patterns, also add remaining for AVX.Bruno Cardoso Lopes2011-08-241-97/+97
| | | | llvm-svn: 138519
* Move remaining MOVDDUP patterns close to MOVDDUP defintion and duplicateBruno Cardoso Lopes2011-08-241-27/+36
| | | | | | the missing ones for AVX. llvm-svn: 138518
* Organize and tidy up MOVDDUP section. Also update comments!Bruno Cardoso Lopes2011-08-241-35/+33
| | | | llvm-svn: 138517
* Move MOVHLPS patterns close to MOVHLPS definition, and duplicate theBruno Cardoso Lopes2011-08-241-6/+10
| | | | | | pattern for 128-bit AVX mode. llvm-svn: 138516
* Move all PSHUF* patterns close to the PSHUF* definitions. Also beBruno Cardoso Lopes2011-08-241-47/+56
| | | | | | | explicit about which subtarget they refer to, and add AVX versions of the ones we currently don't. Remove old and now wrong comments! llvm-svn: 138515
* Move all SHUFP* patterns close to the SHUFP* definitions. Also beBruno Cardoso Lopes2011-08-242-79/+107
| | | | | | | | explicit about which subtarget they refer to, and add AVX versions of the ones we currently don't. Make the mask check more strict, to be clear it won't be used to match to 256-bit versions! llvm-svn: 138514
* Perform more thorough checking of t2IT mask parameters, which fixes all ↵Owen Anderson2011-08-242-0/+14
| | | | | | remaining crashers when disassembling the entire 16-bit instruction space. llvm-svn: 138507
* Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient ↵Eli Friedman2011-08-241-3/+33
| | | | | | implementations eventually. llvm-svn: 138505
* ARM asm backend initialize isThumbMode based on target triple.Jim Grosbach2011-08-241-1/+1
| | | | llvm-svn: 138501
* Thumb .n mnemonic qualifiers can be ignored for now.Jim Grosbach2011-08-241-1/+5
| | | | | | | We'll need to pay attention to them when we start getting more serious about the details of parsing thumb2 assembly. llvm-svn: 138500
* Thumb parsing and encoding for SUB (SP minu immediate).Jim Grosbach2011-08-242-7/+13
| | | | | | | Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that form is Thumb2 only. llvm-svn: 138494
* Be careful not to walk off the end of the operand info list while updating ↵Owen Anderson2011-08-241-1/+2
| | | | | | VFP predicates. llvm-svn: 138492
* Thumb parsing and encoding support for ADD SP instructions.Jim Grosbach2011-08-242-17/+77
| | | | | | | Fix the test FIXME and add parsing support for the ADD (SP plus immediate) and ADD (SP plus register) instruction forms. llvm-svn: 138488
* Fix whitespace.Eli Friedman2011-08-241-8/+8
| | | | llvm-svn: 138487
* Basic x86 code generation for atomic load and store instructions.Eli Friedman2011-08-242-0/+36
| | | | llvm-svn: 138478
* When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate.Jim Grosbach2011-08-241-0/+1
| | | | | | rdar://10015134 llvm-svn: 138467
* Mark VZEROALL as clobbering all YMM registersBruno Cardoso Lopes2011-08-241-3/+7
| | | | llvm-svn: 138461
* Add missing explicit writeback operand to tSTMIA_UPD.Jim Grosbach2011-08-242-4/+5
| | | | | | rdar://10014745 llvm-svn: 138457
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-2492-219/+90
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Thumb add SP assembly syntax fix.Jim Grosbach2011-08-241-2/+2
| | | | llvm-svn: 138448
* Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.Jim Grosbach2011-08-248-39/+39
| | | | | | | | | Add the predicate operand to the instructions. Update the back end accordingly where the instructions are used. Restrict the SP operands to actually only be SP, as otherwise these break assembly parsing for the normal instruction variants. llvm-svn: 138445
* Be stricter in enforcing IT instruction predicate values, so that we don't ↵Owen Anderson2011-08-242-0/+15
| | | | | | end up trying to print out an illegal predicate. llvm-svn: 138443
* Add Uses=[SP] to call instructions. This fixes a miscompilation with aRichard Osborne2011-08-241-2/+2
| | | | | | variable sized alloca. llvm-svn: 138433
* Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid ↵Craig Topper2011-08-242-3/+72
| | | | | | costly scalarization. Fixes PR10711. llvm-svn: 138427
* Fix a nasty bug where a v4i64 was being wrong emitted with 32-bitBruno Cardoso Lopes2011-08-232-55/+106
| | | | | | | permutations. Also tidy up some patterns and make them close to their instruction definition! llvm-svn: 138392
* Move ARM frame-unwinding EHABI handling a touch earlier.Jim Grosbach2011-08-231-4/+4
| | | | | | | | It should go before AsmPrinter MC pseudo expansion since it's based on MachineInstr, not MCInst. Otherwise any frame related pseudo instructions may be missed. llvm-svn: 138386
* [SU]XT[BH] are only available on ARMv6 and up.Jim Grosbach2011-08-231-0/+2
| | | | llvm-svn: 138373
* Some refactoring so TargetRegistry.h no longer has to include any filesEvan Cheng2011-08-2314-5/+32
| | | | | | from MC. llvm-svn: 138367
* Thumb parsing and encoding for SVC.Jim Grosbach2011-08-231-1/+1
| | | | llvm-svn: 138360
* PerformSubCombine to work on integers larger than i128. Fixes a crasher.Nick Lewycky2011-08-231-4/+2
| | | | llvm-svn: 138354
* Thumb parsing and encoding for tSTRspi.Jim Grosbach2011-08-231-0/+2
| | | | llvm-svn: 138348
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