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* Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to ↵Evan Cheng2011-07-2616-49/+45
| | | | | | MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser. llvm-svn: 136027
* Clean up a pile of hacks in our CMake build relating to TableGen.Chandler Carruth2011-07-2639-13/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first problem to fix is to stop creating synthetic *Table_gen targets next to all of the LLVM libraries. These had no real effect as CMake specifies that add_custom_command(OUTPUT ...) directives (what the 'tablegen(...)' stuff expands to) are implicitly added as dependencies to all the rules in that CMakeLists.txt. These synthetic rules started to cause problems as we started more and more heavily using tablegen files from *subdirectories* of the one where they were generated. Within those directories, the set of tablegen outputs was still available and so these synthetic rules added them as dependencies of those subdirectories. However, they were no longer properly associated with the custom command to generate them. Most of the time this "just worked" because something would get to the parent directory first, and run tablegen there. Once run, the files existed and the build proceeded happily. However, as more and more subdirectories have started using this, the probability of this failing to happen has increased. Recently with the MC refactorings, it became quite common for me when touching a large enough number of targets. To add insult to injury, several of the backends *tried* to fix this by adding explicit dependencies back to the parent directory's tablegen rules, but those dependencies didn't work as expected -- they weren't forming a linear chain, they were adding another thread in the race. This patch removes these synthetic rules completely, and adds a much simpler function to declare explicitly that a collection of tablegen'ed files are referenced by other libraries. From that, we can add explicit dependencies from the smaller libraries (such as every architectures Desc library) on this and correctly form a linear sequence. All of the backends are updated to use it, sometimes replacing the existing attempt at adding a dependency, sometimes adding a previously missing dependency edge. Please let me know if this causes any problems, but it fixes a rather persistent and problematic source of build flakiness on our end. llvm-svn: 136023
* Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to ↵Evan Cheng2011-07-2515-62/+52
| | | | | | createMCAsmBackend. llvm-svn: 136010
* ARM assembly parsing and encoding for SSAT16 instruction.Jim Grosbach2011-07-255-6/+32
| | | | llvm-svn: 136006
* Codegen allonesvector better while using AVX: vpcmpeqd + vinsertf128Bruno Cardoso Lopes2011-07-254-13/+58
| | | | | | This also fixes PR10452 llvm-svn: 136004
* Add remaining 256-bit vector bitcasts. This also fixes PR10451Bruno Cardoso Lopes2011-07-251-4/+18
| | | | llvm-svn: 136003
* - Handle special scalar_to_vector case: splats. Using a native 128-bitBruno Cardoso Lopes2011-07-254-1/+65
| | | | | | | | | | shuffle before inserting on a 256-bit vector. - Add AVX versions of movd/movq instructions - Introduce a few COPY patterns to match insert_subvector instructions. This turns a trivial insert_subvector instruction into a register copy, coalescing the xmm into a ymm and avoid emiting on more instruction. llvm-svn: 136002
* Reintroduce r135730, this is indeed the right approach, there is noBruno Cardoso Lopes2011-07-251-0/+18
| | | | | | native 256-bit vector instruction to do scalar_to_vector. llvm-svn: 136001
* Add a note about efficient codegen for binary log.Benjamin Kramer2011-07-251-0/+48
| | | | llvm-svn: 135996
* ARM assembly parsing and encoding for SSAT instruction.Jim Grosbach2011-07-256-63/+122
| | | | | | | | | | | | Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the shift operand to correctly handle the allowed shift types and immediate ranges and issue meaningful diagnostics when an illegal value or shift type is specified. Add aliases to parse an ommitted shift operand (default value of 'lsl #0'). Add tests for diagnostics and proper encoding. llvm-svn: 135990
* Refactoring fail.Evan Cheng2011-07-255-49/+47
| | | | llvm-svn: 135986
* Move CBackend and CppBackend MC initialization to TargetInfo.Evan Cheng2011-07-254-4/+4
| | | | llvm-svn: 135982
* Get rid of an incorrect optimization for shuffles with PALIGNR and simplify ↵Eli Friedman2011-07-251-15/+5
| | | | | | | | isPALIGNRMask. Addresses PR10466, although the crash from that PR only triggers in cases where DAGCombine misses optimizing a shuffle. llvm-svn: 135980
* Fix more MC layering violations.Evan Cheng2011-07-251-2/+9
| | | | llvm-svn: 135979
* More MC layering violations.Evan Cheng2011-07-254-62/+59
| | | | llvm-svn: 135978
* Add LLVMAddTargetLibraryInfo to the C API.Rafael Espindola2011-07-251-0/+6
| | | | llvm-svn: 135975
* Separate MCInstPrinter registration from AsmPrinter registration.Evan Cheng2011-07-2512-65/+81
| | | | llvm-svn: 135974
* Simply ARM so_reg MIOperandInfo definitions.Jim Grosbach2011-07-251-4/+4
| | | | | | | | The shift immediate encoding, printing, etc. is handled directly by the enclosing operand definition, so it should be a vanilla immediate, not a nested complex operand (shift_imm). llvm-svn: 135968
* Fix last bits of MC layer issues. llvm-mc doesn't need to initialize ↵Evan Cheng2011-07-253-28/+12
| | | | | | TargetMachine's anymore. llvm-svn: 135963
* ARM asm operand renaming. Make things a bit more explicit.Jim Grosbach2011-07-252-32/+32
| | | | llvm-svn: 135959
* More simple cleanup of ARM asm operand definitions.Jim Grosbach2011-07-252-28/+13
| | | | llvm-svn: 135958
* Code clean up.Evan Cheng2011-07-255-23/+1
| | | | llvm-svn: 135954
* Refactor MBlaze target to separate MC routines from Target routines.Evan Cheng2011-07-2515-190/+216
| | | | llvm-svn: 135953
* Update the comment. This feature is available only on Darwin at the moment. ↵Bill Wendling2011-07-251-1/+2
| | | | | | Though it's not Darwin-specific. llvm-svn: 135951
* Make assembly parser method names more consistent.Jim Grosbach2011-07-253-28/+28
| | | | llvm-svn: 135950
* Unbreak the build.Oscar Fuentes2011-07-251-0/+1
| | | | llvm-svn: 135949
* Tidy up formatting.Jim Grosbach2011-07-251-50/+18
| | | | | | | | Remove some inititalizers that are the same as the default, move defs next to their (singular) uses and generally simplify some formatting of asm operand definitions. llvm-svn: 135946
* Tidy up a bit.Jim Grosbach2011-07-251-8/+2
| | | | llvm-svn: 135945
* Missed a file.Evan Cheng2011-07-251-0/+70
| | | | llvm-svn: 135943
* Refactor PPC target to separate MC routines from Target routines.Evan Cheng2011-07-2514-97/+57
| | | | llvm-svn: 135942
* More refactoring.Evan Cheng2011-07-259-53/+53
| | | | llvm-svn: 135939
* Refactor X86 target to separate MC code from Target code.Evan Cheng2011-07-2510-553/+587
| | | | llvm-svn: 135930
* Changed disabled code into a flag.Bill Wendling2011-07-251-1/+7
| | | | llvm-svn: 135924
* Remove dead variable.Bill Wendling2011-07-251-1/+0
| | | | llvm-svn: 135923
* After we've modified the prolog to save volatile registers, generate the compactBill Wendling2011-07-252-5/+250
| | | | | | | | | | | unwind encoding for that function. This simply crawls through the prolog looking for machine instrs marked as "frame setup". It can calculate from these what the compact unwind should look like. This is currently disabled because of needed linker support. But initial tests look good. llvm-svn: 135922
* Set PPCII::MO_DARWIN_STUB only on MacOSX < 10.5.Roman Divacky2011-07-241-2/+2
| | | | llvm-svn: 135866
* ARMMCTargetDesc.h: Fixup to add DataTypes.h, or uint32_t would be unavailable.NAKAMURA Takumi2011-07-231-0/+1
| | | | llvm-svn: 135837
* Move TargetAsmParser.h TargetAsmBackend.h and TargetAsmLexer.h to MC where ↵Evan Cheng2011-07-2313-32/+14
| | | | | | they belong. llvm-svn: 135833
* createXXXMCCodeGenInfo should be static.Evan Cheng2011-07-2312-23/+23
| | | | llvm-svn: 135826
* Sink ARM mc routines into MCTargetDesc.Evan Cheng2011-07-2312-67/+77
| | | | llvm-svn: 135825
* ARM SSAT instruction 5-bit immediate handling.Jim Grosbach2011-07-228-23/+37
| | | | | | | | | The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield. Update the representation such that we store the operand as 0-31, allowing us to remove the encoder method and the special case handling in the disassembler. Update the assembly parser and the instruction printer accordingly. llvm-svn: 135823
* ARM assembly parsing and encoding updates.Jim Grosbach2011-07-221-1/+1
| | | | | | Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS. llvm-svn: 135817
* Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,Evan Cheng2011-07-2215-293/+236
| | | | | | InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC. llvm-svn: 135812
* Fix PR10422 by adding the necessary AVX UCOMISD memory versions toBruno Cardoso Lopes2011-07-221-2/+8
| | | | | | load folding logic llvm-svn: 135801
* ARM assembly parsing and encoding of SMLAL instruction.Jim Grosbach2011-07-221-1/+1
| | | | | | Fix parsing of carry-setting variant SMLALS and add tests. llvm-svn: 135797
* ARM encoding and assembly parsing of SMLAD{X} instructions.Jim Grosbach2011-07-221-6/+8
| | | | | | Fix encoding of destination register. Add tests. llvm-svn: 135796
* Add v8f32->v8i32 bitcast. Fixes PR10440Bruno Cardoso Lopes2011-07-221-0/+1
| | | | llvm-svn: 135794
* Turn shuffles into unpacks for VT == MVT::v2i64 and MVT::v2f64Rafael Espindola2011-07-221-9/+5
| | | | | | too. Patch by Jeff Muizelaar. llvm-svn: 135789
* Fix x86's XALUO lowering to return its replacement values insteadDan Gohman2011-07-221-4/+2
| | | | | | | of doing the RAUW calls for the overflow value itself. This makes it more consistent with how the rest of LegalizeDAG works. llvm-svn: 135788
* Fix test failures caused by my so_reg refactoring.Owen Anderson2011-07-221-2/+2
| | | | llvm-svn: 135785
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