| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | Hide the call to InitMCInstrInfo into tblgen generated ctor. | Evan Cheng | 2011-07-01 | 2 | -3/+6 | |
| | | | | | llvm-svn: 134244 | |||||
| * | Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to | Evan Cheng | 2011-06-30 | 4 | -6/+8 | |
| | | | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! llvm-svn: 134127 | |||||
| * | Move XCore from getRegClassForInlineAsmConstraint to | Eric Christopher | 2011-06-29 | 2 | -17/+14 | |
| | | | | | | | | | getRegForInlineAsmConstraint. Part of rdar://9643582 llvm-svn: 134080 | |||||
| * | Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo. | Evan Cheng | 2011-06-28 | 2 | -3/+3 | |
| | | | | | llvm-svn: 134030 | |||||
| * | Hide more details in tablegen generated MCRegisterInfo ctor function. | Evan Cheng | 2011-06-28 | 1 | -2/+1 | |
| | | | | | llvm-svn: 134027 | |||||
| * | Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc | Evan Cheng | 2011-06-28 | 4 | -6/+8 | |
| | | | | | llvm-svn: 134024 | |||||
| * | Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc | Evan Cheng | 2011-06-27 | 5 | -9/+10 | |
| | | | | | | | into XXXGenRegisterInfo.inc. llvm-svn: 133922 | |||||
| * | Fix cmake build. | Rafael Espindola | 2011-06-24 | 1 | -0/+1 | |
| | | | | | llvm-svn: 133830 | |||||
| * | Starting to refactor Target to separate out code that's needed to fully describe | Evan Cheng | 2011-06-24 | 3 | -9/+9 | |
| | | | | | | | | | | | | | target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. llvm-svn: 133782 | |||||
| * | Fix a FIXME by making GlobalVariable::getInitializer() return a | Jay Foad | 2011-06-19 | 1 | -1/+1 | |
| | | | | | | | const Constant *. llvm-svn: 133400 | |||||
| * | Use set operations instead of plain lists to enumerate register classes. | Jakob Stoklund Olesen | 2011-06-15 | 1 | -3/+3 | |
| | | | | | | | | | | | | | This simplifies many of the target description files since it is common for register classes to be related or contain sequences of numbered registers. I have verified that this doesn't change the files generated by TableGen for ARM and X86. It alters the allocation order of MBlaze GPR and Mips FGR32 registers, but I believe the change is benign. llvm-svn: 133105 | |||||
| * | Remove custom allocation order boilerplate that is no longer needed. | Jakob Stoklund Olesen | 2011-06-09 | 1 | -21/+1 | |
| | | | | | | | | | | | | | | | | | | | | | The register allocators automatically filter out reserved registers and place the callee saved registers last in the allocation order, so custom methods are no longer necessary just for that. Some targets still use custom allocation orders: ARM/Thumb: The high registers are removed from GPR in thumb mode. The NEON allocation orders prefer to use non-VFP2 registers first. X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble. SystemZ: Some of the allocation orders are omitting R12 aliases without explanation. I don't understand this target well enough to fix that. It looks like all the boilerplate could be removed by reserving the right registers. llvm-svn: 132781 | |||||
| * | Add a parameter to CCState so that it can access the MachineFunction. | Eric Christopher | 2011-06-08 | 2 | -13/+14 | |
| | | | | | | | | | No functional change. Part of PR6965 llvm-svn: 132763 | |||||
| * | Flag unallocatable register classes instead of giving them empty | Jakob Stoklund Olesen | 2011-06-02 | 1 | -18/+3 | |
| | | | | | | | allocation orders. llvm-svn: 132509 | |||||
| * | Fix 80 column violations. | Richard Osborne | 2011-05-31 | 1 | -2/+5 | |
| | | | | | llvm-svn: 132341 | |||||
| * | Add XCore intrinsic for crc8. | Richard Osborne | 2011-05-31 | 2 | -0/+16 | |
| | | | | | llvm-svn: 132340 | |||||
| * | Add XCore intrinsic for crc32. | Richard Osborne | 2011-05-31 | 1 | -1/+7 | |
| | | | | | llvm-svn: 132336 | |||||
| * | Use the dwarf->llvm mapping to print register names in the cfi | Rafael Espindola | 2011-05-30 | 2 | -0/+5 | |
| | | | | | | | | | directives. Fixes PR9826. llvm-svn: 132317 | |||||
| * | Replace the -unwind-tables option with a per function flag. This is more | Rafael Espindola | 2011-05-25 | 1 | -2/+2 | |
| | | | | | | | | LTO friendly as we can now correctly merge files compiled with or without -fasynchronous-unwind-tables. llvm-svn: 132033 | |||||
| * | Remove dead code. | Devang Patel | 2011-05-24 | 1 | -3/+0 | |
| | | | | | llvm-svn: 131974 | |||||
| * | Make the logic for determining function alignment more explicit. No ↵ | Eli Friedman | 2011-05-06 | 2 | -9/+2 | |
| | | | | | | | functionality change. llvm-svn: 131012 | |||||
| * | Remove unused STL header includes. | Jay Foad | 2011-04-23 | 2 | -4/+0 | |
| | | | | | llvm-svn: 130068 | |||||
| * | Fix a ton of comment typos found by codespell. Patch by | Chris Lattner | 2011-04-15 | 1 | -1/+1 | |
| | | | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558 | |||||
| * | Add XCore intrinsics for initializing / starting / synchronizing threads. | Richard Osborne | 2011-03-31 | 1 | -6/+39 | |
| | | | | | llvm-svn: 128633 | |||||
| * | Add XCore intrinsic for setpsc. | Richard Osborne | 2011-03-17 | 1 | -1/+5 | |
| | | | | | llvm-svn: 127821 | |||||
| * | Add XCore intrinsics for setclk, setrdy. | Richard Osborne | 2011-03-16 | 1 | -1/+9 | |
| | | | | | llvm-svn: 127761 | |||||
| * | Add checkevent intrinsic to check if any resources owned by the current thread | Richard Osborne | 2011-03-16 | 2 | -55/+134 | |
| | | | | | | | can event. llvm-svn: 127741 | |||||
| * | Don't indent cases in a switch, no functionality change. | Richard Osborne | 2011-03-15 | 1 | -50/+50 | |
| | | | | | llvm-svn: 127681 | |||||
| * | On the XCore the scavenging slot should be closest to the SP. | Richard Osborne | 2011-03-15 | 2 | -0/+7 | |
| | | | | | llvm-svn: 127680 | |||||
| * | Add XCore intrinsics for getps, setps, setsr and clrsr. | Richard Osborne | 2011-03-15 | 1 | -3/+25 | |
| | | | | | llvm-svn: 127678 | |||||
| * | Allow targets to specify a the type of the RHS of a shift parameterized on ↵ | Owen Anderson | 2011-02-25 | 2 | -74/+74 | |
| | | | | | | | the type of the LHS. llvm-svn: 126518 | |||||
| * | Add XCore intrinsic for eeu instruction. | Richard Osborne | 2011-02-24 | 1 | -0/+4 | |
| | | | | | llvm-svn: 126384 | |||||
| * | Add XCore intrinsic for clre instruction. | Richard Osborne | 2011-02-23 | 1 | -1/+3 | |
| | | | | | llvm-svn: 126322 | |||||
| * | Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable | Richard Osborne | 2011-02-23 | 1 | -1/+7 | |
| | | | | | | | | events on the thread and wait until a resource is ready to event. The vector of the resource that is ready is returned. llvm-svn: 126320 | |||||
| * | Add XCore intrinsic for the setv instruction. | Richard Osborne | 2011-02-23 | 1 | -1/+6 | |
| | | | | | llvm-svn: 126315 | |||||
| * | Fix format for setc instruction. | Richard Osborne | 2011-02-23 | 1 | -1/+1 | |
| | | | | | llvm-svn: 126314 | |||||
| * | Add XCore intrinsic for settw instruction. | Richard Osborne | 2011-02-23 | 1 | -1/+5 | |
| | | | | | llvm-svn: 126313 | |||||
| * | Add XCore intrinsics for various instructions on ports. | Richard Osborne | 2011-02-21 | 1 | -2/+24 | |
| | | | | | llvm-svn: 126132 | |||||
| * | Use explicit add_subdirectory's for LLVM target sublibraries instead | Oscar Fuentes | 2011-02-20 | 1 | -0/+2 | |
| | | | | | | | | | | of testing for its presence at cmake time. This way the build automatically regenerates the makefiles when a svn update brings in a new sublibrary. llvm-svn: 126068 | |||||
| * | Swap VT and DebugLoc operands of getExtLoad() for consistency with | Stuart Hastings | 2011-02-16 | 1 | -2/+2 | |
| | | | | | | | other getNode() methods. Radar 9002173. llvm-svn: 125665 | |||||
| * | Add intrinsic for setc instruction on the XCore. | Richard Osborne | 2011-02-09 | 1 | -1/+12 | |
| | | | | | llvm-svn: 125186 | |||||
| * | Add XCore intrinsics for resource instructions. | Richard Osborne | 2011-02-03 | 1 | -4/+51 | |
| | | | | | llvm-svn: 124794 | |||||
| * | Add support for trampolines on the XCore. | Richard Osborne | 2011-02-02 | 4 | -1/+72 | |
| | | | | | llvm-svn: 124722 | |||||
| * | Remove more duplicated code. | Rafael Espindola | 2011-01-23 | 1 | -12/+12 | |
| | | | | | llvm-svn: 124056 | |||||
| * | Remove duplicated code. | Rafael Espindola | 2011-01-23 | 1 | -6/+7 | |
| | | | | | llvm-svn: 124054 | |||||
| * | Fix a few more places that should use MBB::getLastNonDebugInstr(). | Jakob Stoklund Olesen | 2011-01-13 | 1 | -1/+1 | |
| | | | | | llvm-svn: 123408 | |||||
| * | Update CMake stuff | Anton Korobeynikov | 2011-01-10 | 1 | -1/+1 | |
| | | | | | llvm-svn: 123171 | |||||
| * | Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵ | Anton Korobeynikov | 2011-01-10 | 7 | -32/+33 | |
| | | | | | | | and fixes here and there. llvm-svn: 123170 | |||||
| * | Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpy | Evan Cheng | 2011-01-06 | 1 | -2/+3 | |
| | | | | | | | | etc. takes an option OptSize. If OptSize is true, it would return the inline limit for functions with attribute OptSize. llvm-svn: 122952 | |||||
| * | Flag -> Glue, the ongoing saga | Chris Lattner | 2010-12-23 | 1 | -4/+4 | |
| | | | | | llvm-svn: 122513 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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