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* Xcore targetRobert Lytton2013-08-011-6/+9
| | | | | | Fix emitArrayBound() calling OutStreamer.Emit*() multiple times when trying to print a single line llvm-svn: 187562
* test commitRobert Lytton2013-07-291-0/+1
| | | | llvm-svn: 187348
* test commitRichard Osborne2013-07-261-1/+1
| | | | llvm-svn: 187195
* [XCore] Add TODO regarding byval structsRichard Osborne2013-07-261-0/+2
| | | | llvm-svn: 187193
* [XCore] Ensure implicit operands aren't lost on the return instruction.Richard Osborne2013-07-171-1/+3
| | | | | | Patch by Robert Lytton. llvm-svn: 186500
* [XCore] Fix printing of inline asm operands.Richard Osborne2013-07-161-11/+7
| | | | | | | Previously an asm operand with no operand modifier would give the error "invalid operand in inline asm". llvm-svn: 186407
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-141-4/+4
| | | | | | size. llvm-svn: 186274
* [XCore] Whitespace fixes, no functionality change.Richard Osborne2013-07-031-3/+3
| | | | llvm-svn: 185519
* [XCore] Add ISel pattern for LDWCPRichard Osborne2013-07-031-8/+7
| | | | | | Patch by Robert Lytton. llvm-svn: 185518
* [XCore] Fix instruction selection for zext, mkmsk instructions.Richard Osborne2013-07-022-2/+2
| | | | | | | | | | | r182680 replaced CountLeadingZeros_32 with a template function countLeadingZeros that relies on using the correct argument type to give the right result. The type passed in the XCore backend after this revision was incorrect in a couple of places. Patch by Robert Lytton. llvm-svn: 185430
* The getRegForInlineAsmConstraint function should only accept MVT value types.Chad Rosier2013-06-222-2/+2
| | | | llvm-svn: 184642
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-191-3/+1
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184360
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE ↵David Blaikie2013-06-163-53/+2
| | | | | | | | | | MachineInstrs Frame index handling is now target-agnostic, so delete the target hooks for creation & asm printing of target-specific addressing in DBG_VALUEs and any related functions. llvm-svn: 184067
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-073-6/+6
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183572
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-061-1/+1
| | | | | | | Caching it as a pointer allows us to reset it if the TargetMachine object changes. llvm-svn: 183361
* Order CALLSEQ_START and CALLSEQ_END nodes.Andrew Trick2013-05-291-2/+2
| | | | | | | | | | | | Fixes PR16146: gdb.base__call-ar-st.exp fails after pre-RA-sched=source fixes. Patch by Xiaoyi Guo! This also fixes an unsupported dbg.value test case. Codegen was previously incorrect but the test was passing by luck. llvm-svn: 182885
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-253-35/+35
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.Michael J. Spencer2013-05-242-3/+3
| | | | llvm-svn: 182680
* Remove the Copied parameter from MemoryObject::readBytes.Benjamin Kramer2013-05-241-2/+2
| | | | | | | | | | There was exactly one caller using this API right, the others were relying on specific behavior of the default implementation. Since it's too hard to use it right just remove it and standardize on the default behavior. Defines away PR16132. llvm-svn: 182636
* Removed unused variable, detected by gccPatrik Hagglund2013-05-161-2/+0
| | | | | | -Wunused-but-set-variable. Leftover from r181979. llvm-svn: 181993
* Don't call addFrameMove on XCore.Rafael Espindola2013-05-161-34/+0
| | | | | | | | getExceptionHandlingType is not ExceptionHandling::DwarfCFI on xcore, so etFrameInstructions is never called. There is no point creating cfi instructions if they are never used. llvm-svn: 181979
* Remove the MachineMove class.Rafael Espindola2013-05-132-4/+5
| | | | | | | | | | | | It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. llvm-svn: 181680
* Change getFrameMoves to return a const reference.Rafael Espindola2013-05-111-8/+6
| | | | | | | To add a frame now there is a dedicated addFrameMove which also takes care of constructing the move itself. llvm-svn: 181657
* Remove unused argument.Rafael Espindola2013-05-103-4/+4
| | | | llvm-svn: 181618
* [XCore] Fix handling of functions where only the LR is spilled.Richard Osborne2013-05-091-27/+30
| | | | | | | | | | | | | | Previously we only checked if the LR required saving if the frame size was non zero. However because the caller reserves 1 word for the callee to use that doesn't count towards our frame size it is possible for the LR to need saving and for the frame size to be 0. We didn't hit when the LR needed saving because of a function calls because the 1 word of stack we must allocate for our callee means the frame size is always non zero in this case. However we can hit this case if the LR is clobbered in inline asm. llvm-svn: 181520
* [XCore] Add LDAPB instructions.Richard Osborne2013-05-051-3/+13
| | | | | | | With the change the disassembler now supports the XCore ISA in its entirety. llvm-svn: 181155
* [XCore] Update LDAP to use pcrel_imm.Richard Osborne2013-05-051-3/+3
| | | | llvm-svn: 181154
* [XCore] Rename calltarget -> pcrel_imm.Richard Osborne2013-05-051-6/+6
| | | | | | No functionality change. llvm-svn: 181153
* [XCore] Add BLRB instructions.Richard Osborne2013-05-051-0/+7
| | | | llvm-svn: 181152
* [XCore] Remove '-' from back branch asm syntax.Richard Osborne2013-05-052-6/+18
| | | | | | | | Instead operands are treated as negative immediates where the sign bit is implicit in the instruction encoding. llvm-svn: 181151
* Fix buildbot failure on 64 bit linux due to std::max() having differentRichard Osborne2013-05-041-1/+1
| | | | | | operand types. llvm-svn: 181128
* [XCore] Remove unused operand type.Richard Osborne2013-05-041-1/+0
| | | | llvm-svn: 181127
* [XCore] Make use of the target independent global address offset folding.Richard Osborne2013-05-046-98/+41
| | | | | | | | This let us to remove some custom code that matched constant offsets from globals at instruction selection time as a special addressing mode. No intended functionality change. llvm-svn: 181126
* [XCore] Simplify code that checks for an aligned base plus a constant.Richard Osborne2013-05-042-81/+56
| | | | | | | | | The code now makes use of ComputeMaskedBits, SelectionDAG::isBaseWithConstantOffset and TargetLowering::isGAPlusOffset where appropriate reducing the amount of logic needed in XCoreISelLowering. No intended functionality change. llvm-svn: 181125
* [XCore] Move lowering of thread local storage to a separate pass.Richard Osborne2013-05-046-55/+158
| | | | | | | | | | | | | Thread local storage is not supported by the XMOS linker so we handle thread local variables by lowering the variable to an array of n elements (where n is the number of hardware threads per core, currently 8 for all XMOS devices) indexed by the the current thread ID. Previously this lowering was spread across the XCoreISelLowering and the XCoreAsmPrinter classes. Moving this to a separate pass should be much cleaner. llvm-svn: 181124
* [XCore] Use static relocation model by default.Richard Osborne2013-05-044-5/+11
| | | | | | | This allows us to get get rid of a hack in XCoreTargetObjectFile where the the DataRel* sections were overridden. llvm-svn: 181116
* ArrayRefize getMachineNode(). No functionality change.Michael Liao2013-04-191-6/+6
| | | | llvm-svn: 179901
* [XCore] Add bru instruction.Richard Osborne2013-04-041-0/+3
| | | | llvm-svn: 178783
* [XCore] The RRegs register class is a superset of GRRegs.Richard Osborne2013-04-044-34/+46
| | | | | | | | | | At the time when the XCore backend was added there were some issues with with overlapping register classes but these all seem to be fixed now. Describing the register classes correctly allow us to get rid of a codegen only instruction (LDAWSP_lru6_RRegs) and it means we can disassemble ru6 instructions that use registers above r11. llvm-svn: 178782
* Allow the register scavenger to spill multiple registersHal Finkel2013-03-221-1/+1
| | | | | | | | | | | | | | | | | | This patch lets the register scavenger make use of multiple spill slots in order to guarantee that it will be able to provide multiple registers simultaneously. To support this, the RS's API has changed slightly: setScavengingFrameIndex / getScavengingFrameIndex have been replaced by addScavengingFrameIndex / isScavengingFrameIndex / getScavengingFrameIndices. In forthcoming commits, the PowerPC backend will use this capability in order to implement the spilling of condition registers, and some special-purpose registers, without relying on r0 being reserved. In some cases, spilling these registers requires two GPRs: one for addressing and one to hold the value being transferred. llvm-svn: 177774
* DAGCombiner: Use correct value type for checking legality of BR_CC v3Tom Stellard2013-03-081-1/+1
| | | | | | | | | | | | | LegalizeDAG.cpp uses the value of the comparison operands when checking the legality of BR_CC, so DAGCombiner should do the same. v2: - Expand more BR_CC value types for NVPTX v3: - Expand correct BR_CC value types for Hexagon, Mips, and XCore. llvm-svn: 176694
* Fix PR10475Michael Liao2013-03-011-1/+1
| | | | | | | | | | | | | | - ISD::SHL/SRL/SRA must have either both scalar or both vector operands but TLI.getShiftAmountTy() so far only return scalar type. As a result, backend logic assuming that breaks. - Rename the original TLI.getShiftAmountTy() to TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to return target-specificed scalar type or the same vector type as the 1st operand. - Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar type. llvm-svn: 176364
* Move the eliminateCallFramePseudoInstr method from TargetRegisterInfoEli Bendersky2013-02-214-56/+56
| | | | | | | | | | | | | | | to TargetFrameLowering, where it belongs. Incidentally, this allows us to delete some duplicated (and slightly different!) code in TRI. There are potentially other layering problems that can be cleaned up as a result, or in a similar manner. The refactoring was OK'd by Anton Korobeynikov on llvmdev. Note: this touches the target interfaces, so out-of-tree targets may be affected. llvm-svn: 175788
* Update TargetLowering ivars for name policy.Jim Grosbach2013-02-201-3/+3
| | | | | | | | | | | http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly ivars should be camel-case and start with an upper-case letter. A few in TargetLowering were starting with a lower-case letter. No functional change intended. llvm-svn: 175667
* [XCore] Add missing 2r instructions.Richard Osborne2013-02-173-1/+35
| | | | | | | These instructions are not targeted by the compiler but it is needed for the MC layer. llvm-svn: 175407
* [XCore] Add TSETR instruction.Richard Osborne2013-02-173-1/+34
| | | | | | | This instruction is not targeted by the compiler but it is needed for the MC layer. llvm-svn: 175406
* [XCore] Add missing u10 / lu10 instructions.Richard Osborne2013-02-171-1/+12
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. llvm-svn: 175404
* [XCore] Add missing u6 / lu6 instructions.Richard Osborne2013-02-171-2/+18
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. llvm-svn: 175403
* Move MRI liveouts to XCore return instructions.Jakob Stoklund Olesen2013-02-052-16/+14
| | | | llvm-svn: 174414
* [PEI] Pass the frame index operand number to the eliminateFrameIndex function.Chad Rosier2013-01-312-14/+9
| | | | | | | Each target implementation was needlessly recomputing the index. Part of rdar://13076458 llvm-svn: 174083
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