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* [PEI] Pass the frame index operand number to the eliminateFrameIndex function.Chad Rosier2013-01-312-16/+12
| | | | | | | Each target implementation was needlessly recomputing the index. Part of rdar://13076458 llvm-svn: 174083
* Whitespace.Eric Christopher2013-01-311-9/+9
| | | | llvm-svn: 174009
* Check and allow floating point registers to select the size of theEric Christopher2013-01-311-2/+2
| | | | | | | register for inline asm. This conforms to how gcc allows for effective casting of inputs into gprs (fprs is already handled). llvm-svn: 174008
* Restrict sin/cos optimization to 64-bit only for now. 32-bit is a bit messy ↵Evan Cheng2013-01-302-10/+14
| | | | | | and less critical. llvm-svn: 173987
* Remove dead code.Evan Cheng2013-01-291-10/+0
| | | | llvm-svn: 173812
* Fix typo in X86BaseInfo.h that I introduced in r157818.Hans Wennborg2013-01-291-2/+2
| | | | llvm-svn: 173798
* Merge SSE and AVX shuffle instructions in the comment printer.Craig Topper2013-01-291-98/+14
| | | | llvm-svn: 173777
* Teach SDISel to combine fsin / fcos into a fsincos node if the followingEvan Cheng2013-01-294-15/+91
| | | | | | | | | | | | | | | | | | conditions are met: 1. They share the same operand and are in the same BB. 2. Both outputs are used. 3. The target has a native instruction that maps to ISD::FSINCOS node or the target provides a sincos library call. Implemented the generic optimization in sdisel and enabled it for Mac OSX. Also added an additional optimization for x86_64 Mac OSX by using an alternative entry point __sincos_stret which returns the two results in xmm0 / xmm1. rdar://13087969 PR13204 llvm-svn: 173755
* Fix 256-bit PALIGNR comment decoding to understand that it works on ↵Craig Topper2013-01-281-2/+11
| | | | | | independent 256-bit lanes. llvm-svn: 173674
* Add missing break in 256-bit palignr comment printing. No test case yet ↵Craig Topper2013-01-281-0/+1
| | | | | | because the comment itself is still wrong. llvm-svn: 173669
* Fix inconsistent usage of PALIGN and PALIGNR when referring to the same ↵Craig Topper2013-01-287-34/+35
| | | | | | instruction. llvm-svn: 173667
* X86: Decode PALIGN operands so I don't have to do it in my head.Benjamin Kramer2013-01-264-1/+36
| | | | llvm-svn: 173572
* X86: Do splat promotion later, so the optimizer can chew on it first.Benjamin Kramer2013-01-261-10/+10
| | | | | | | | | | | | This catches many cases where we can emit a more efficient shuffle for a specific mask or when the mask contains undefs. Once the splat is lowered to unpacks we can't do that anymore. There is a possibility of moving the promotion after pshufb matching, but I'm not sure if pshufb with a mask loaded from memory is faster than 3 shuffles, so I avoided that for now. llvm-svn: 173569
* In this patch, we teach X86_64TargetMachine that it has a ILP32Eli Bendersky2013-01-254-18/+39
| | | | | | | | | | | | | | | | | | | | | (defined by the x32 ABI) mode, in which case its pointers are 32-bits in size. This knowledge is also added to X86RegisterInfo that now returns the appropriate registers in getPointerRegClass. There are many outcomes to this change. In order to keep the patches separate and manageable, we start by focusing on some simple testable cases. The patch adds a test with passing a pointer to a function - focusing on the difference between the two data models for x86-64. Another test is added for handling of 'sret' arguments (and functionality is added in X86ISelLowering to make it work). A note on naming: the "x32 ABI" document refers to the AMD64 architecture (in LLVM it's distinguished by being is64Bits() in the x86 subtarget) with two variations: the LP64 (default) data model, and the ILP32 data model. This patch adds predicates to the subtarget which are consistent with this naming scheme. llvm-svn: 173503
* Moving Cost Tables up to share with other targetsRenato Golin2013-01-241-48/+11
| | | | llvm-svn: 173382
* Fix an issue of pseudo atomic instruction DAG scheduleMichael Liao2013-01-222-3/+8
| | | | | | | | | | - Add list of physical registers clobbered in pseudo atomic insts Physical registers are clobbered when pseudo atomic instructions are expanded. Add them in clobber list to prevent DAG scheduler to mis-schedule them after these insns are declared side-effect free. - Add test case from Michael Kuperstein <michael.m.kuperstein@intel.com> llvm-svn: 173200
* X86: Make sure we account for the FMA4 register immediate value, otherwise ↵Benjamin Kramer2013-01-221-1/+1
| | | | | | | | rip-rel relocations will be off by one byte. PR15040. llvm-svn: 173176
* Initial patch for x32 ABI support.Eli Bendersky2013-01-221-3/+11
| | | | | | | | Add the x32 environment kind to the triple, and separate the concept of pointer size and callee save stack slot size, since they're not equal on x32. llvm-svn: 173175
* Make APFloat constructor require explicit semantics.Tim Northover2013-01-221-18/+30
| | | | | | | | | Previously we tried to infer it from the bit width size, with an added IsIEEE argument for the PPC/IEEE 128-bit case, which had a default value. This default value allowed bugs to creep in, where it was inappropriate. llvm-svn: 173138
* Use <0 checks in place of ==-1 because it results in simpler code.Craig Topper2013-01-211-3/+3
| | | | llvm-svn: 173010
* Use MVT instead of EVT in LowerVECTOR_SHUFFLEtoBlend.Craig Topper2013-01-211-6/+5
| | | | llvm-svn: 173009
* Remove trailing whitespace.Craig Topper2013-01-211-9/+9
| | | | llvm-svn: 173008
* Fix some 80 column violations.Craig Topper2013-01-211-7/+9
| | | | llvm-svn: 173006
* Make helper method static.Craig Topper2013-01-212-4/+2
| | | | llvm-svn: 173005
* Convert more EVT's to MVT's in the lowering methods.Craig Topper2013-01-201-23/+24
| | | | llvm-svn: 172995
* Capitalize lowerTRUNCATE so that it matches the other lower functions in ↵Craig Topper2013-01-202-3/+3
| | | | | | this file despite it not matching coding standards. llvm-svn: 172994
* Revert CostTable algorithm, will re-writeRenato Golin2013-01-201-66/+102
| | | | llvm-svn: 172992
* Make LowerVSETCC a static function and use MVT instead of EVT.Craig Topper2013-01-202-63/+65
| | | | llvm-svn: 172969
* Revert 172708.Nadav Rotem2013-01-201-26/+2
| | | | | | | | | The optimization handles esoteric cases but adds a lot of complexity both to the X86 backend and to other backends. This optimization disables an important canonicalization of chains of SEXT nodes and makes SEXT and ZEXT asymmetrical. Disabling the canonicalization of consecutive SEXT nodes into a single node disables other DAG optimizations that assume that there is only one SEXT node. The AVX mask optimizations is one example. Additionally this optimization does not update the cost model. llvm-svn: 172968
* Make some helper methods static.Craig Topper2013-01-202-9/+3
| | | | llvm-svn: 172936
* Remove DebugLoc argument from static function. It can easily be obtained ↵Craig Topper2013-01-201-4/+5
| | | | | | from the SVOp passed in. llvm-svn: 172935
* Use MVT instead of EVT in more instruction lowering code.Craig Topper2013-01-201-17/+17
| | | | llvm-svn: 172933
* Use MVT instead of EVT in more of the shuffle lowering code.Craig Topper2013-01-191-15/+15
| | | | llvm-svn: 172930
* Capitalize LowerVectorIntExtend to be consistent with all the other lower ↵Craig Topper2013-01-192-3/+3
| | | | | | functions in this file. llvm-svn: 172927
* On Sandybridge split unaligned 256bit stores into two xmm-sized stores. Nadav Rotem2013-01-191-9/+18
| | | | llvm-svn: 172894
* Use MVT instead of EVT when computing shuffle immediates since they can only ↵Craig Topper2013-01-191-10/+10
| | | | | | be for legal types. Keeps compiler from generating unneeded checks and handling for extended types. llvm-svn: 172893
* On Sandybridge loading unaligned 256bits using two XMM loads (vmovups and ↵Nadav Rotem2013-01-181-1/+31
| | | | | | vinsertf128) is faster than using a single vmovups instruction. llvm-svn: 172868
* Calculate vector element size more directly for VINSERTF128/VEXTRACTF128 ↵Craig Topper2013-01-181-6/+4
| | | | | | immediate handling. Also use MVT since this only called on legal types during pattern matching. llvm-svn: 172797
* Minor formatting fix. No functional change.Craig Topper2013-01-181-1/+1
| | | | llvm-svn: 172795
* Spelling fix: extened->extended. Trailing whitespace in same function.Craig Topper2013-01-181-5/+6
| | | | llvm-svn: 172793
* Make more use of is128BitVector/is256BitVector in place of getSizeInBits() ↵Craig Topper2013-01-181-35/+31
| | | | | | == 128/256. llvm-svn: 172792
* [ms-inline asm] Make the error message more generic now that we support the Chad Rosier2013-01-181-1/+1
| | | | | | 'SIZE' and 'LENGTH' operators. llvm-svn: 172773
* [ms-inline asm] Add support for the 'SIZE' and 'LENGTH' operators.Chad Rosier2013-01-171-36/+46
| | | | | | Part of rdar://12576868 llvm-svn: 172743
* Optimization for the following SIGN_EXTEND pairs:Elena Demikhovsky2013-01-171-2/+25
| | | | | | | | | | | | v8i8 -> v8i64, v8i8 -> v8i32, v4i8 -> v4i64, v4i16 -> v4i64 for AVX and AVX2. Bug 14865. llvm-svn: 172708
* Combine AVX and SSE forms of MOVSS and MOVSD into the same multiclasses so ↵Craig Topper2013-01-171-74/+50
| | | | | | they get instantiated together. llvm-svn: 172704
* Provide a place for targets to insert ILP optimization passes.Jakob Stoklund Olesen2013-01-171-6/+10
| | | | | | | | | | | | | | Move the early if-conversion pass into this group. ILP optimizations usually need to find the right balance between register pressure and ILP using the MachineTraceMetrics analysis to identify critical paths and estimate other costs. Such passes should run together so they can share dominator tree and loop info analyses. Besides if-conversion, future passes to run here here could include expression height reduction and ARM's MLxExpansion pass. llvm-svn: 172687
* Change CostTable model to be global to all targetsRenato Golin2013-01-161-102/+66
| | | | | | | | Moving the X86CostTable to a common place, so that other back-ends can share the code. Also simplifying it a bit and commoning up tables with one and two types on operations. llvm-svn: 172658
* [ms-inline asm] Extend support for parsing Intel bracketed memory operands thatChad Rosier2013-01-141-86/+277
| | | | | | | have an arbitrary ordering of the base register, index register and displacement. rdar://12527141 llvm-svn: 172484
* Simplify nested strconcats in X86 td files since strconcat can take more ↵Craig Topper2013-01-142-32/+32
| | | | | | than 2 arguments. llvm-svn: 172379
* Create a single multiclass for SSE and AVX version of MOVL/MOVH. Prevents ↵Craig Topper2013-01-141-23/+24
| | | | | | needing to specify everything twice. No functional change intended llvm-svn: 172378
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