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* Silence a 'enum and non-enum used in conditional' warning.Simon Pilgrim2017-05-031-1/+1
| | | | llvm-svn: 302048
* [X86][LWP] Add llvm support for LWP instructions (reapplied).Simon Pilgrim2017-05-037-0/+88
| | | | | | | | | | This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4). Reapplied - this time without changing line endings of existing files. Differential Revision: https://reviews.llvm.org/D32769 llvm-svn: 302041
* Revert rL302028 due to accidental line ending changes.Simon Pilgrim2017-05-037-750/+662
| | | | llvm-svn: 302038
* [X86][LWP] Add llvm support for LWP instructions.Simon Pilgrim2017-05-037-662/+750
| | | | | | | | This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4). Differential Revision: https://reviews.llvm.org/D32769 llvm-svn: 302028
* [X86][AVX512] remove unnecessary case. NFCGuy Blank2017-05-031-2/+1
| | | | | | | | VFPCLASS is for vector types and not scalar, so it cannot get here. Differential Revision: https://reviews.llvm.org/D32694 llvm-svn: 302023
* [X86] Support of no_caller_saved_registers attributeOren Ben Simhon2017-05-033-8/+40
| | | | | | | | | This patch implements the LLVM part for no_caller_saved_registers attribute as appears here: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=5ed3cc7b66af4758f7849ed6f65f4365be8223be. In order to implement the attribute, we use the dynamic CSR mechanism to remove returned/passed arguments from the function regmask/CSR list. Differential Revision: https://reviews.llvm.org/D31876 llvm-svn: 302020
* [X86] Refactored LowerINTRINSIC_W_CHAIN to use a switch statament. NFCI.Simon Pilgrim2017-05-031-7/+9
| | | | | | Pre-commit as requested in D32769. llvm-svn: 302010
* [X86] Tidyup subvector insert/extract helpers. NFCI.Simon Pilgrim2017-05-021-24/+9
| | | | | | Use getConstantOperandVal where possible. llvm-svn: 301912
* Fix typo in comment. NFCI.Simon Pilgrim2017-05-021-2/+2
| | | | llvm-svn: 301911
* [X86] Reduce code for setting operations actions by merging into loops ↵Simon Pilgrim2017-05-011-129/+68
| | | | | | across multiple types/ops. NFCI. llvm-svn: 301879
* [X86][AVX] Rename LowerVectorBroadcast to lowerBuildVectorAsBroadcast. NFCI.Simon Pilgrim2017-05-011-11/+8
| | | | | | Since the shuffle refactor, this is only used during BUILD_VECTOR lowering. llvm-svn: 301834
* X86: initialize a few subtarget variables.Tim Northover2017-05-011-0/+3
| | | | | | Otherwise an indeterminate value gets read, causing a bunch of UBSan failures. llvm-svn: 301819
* Generalize the specialized flag-carrying SDNodes by moving flags into SDNode.Amara Emerson2017-05-011-10/+8
| | | | | | | | This removes BinaryWithFlagsSDNode, and flags are now all passed by value. Differential Revision: https://reviews.llvm.org/D32527 llvm-svn: 301803
* [GlobalISel][X86] Prioritize Tablegen-erated instruction selection. NFCIgor Breger2017-05-011-50/+8
| | | | | | | | | | | | | | | | Summary: Prioritizes Tablegen-erated instruction selection over C++ instruction selection. Remove G_ADD/G_SUB C++ selection - implemented by Tablegen. Reviewers: dsanders, zvi, guyblank Reviewed By: guyblank Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32677 llvm-svn: 301792
* [GlobalISel][X86] G_SEXT/G_ZEXT support.Igor Breger2017-05-011-0/+20
| | | | | | | | | | | | Reviewers: zvi, guyblank Reviewed By: zvi Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32591 llvm-svn: 301790
* [GlobalISel][X86] G_LOAD/G_STORE pointer selection support.Igor Breger2017-05-011-2/+2
| | | | | | | | | | | | | | Summary: [GlobalISel][X86] G_LOAD/G_STORE pointer selection support. Reviewers: zvi, guyblank Reviewed By: zvi, guyblank Subscribers: dberris, rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D32217 llvm-svn: 301788
* Do not legalize large add with addc/adde, introduce addcarry and do it with ↵Amaury Sechet2017-04-302-0/+65
| | | | | | | | | | | | | | uaddo/addcarry Summary: As per discution on how to get better codegen an large int legalization, it became clear that using a glue for the carry was preventing several desirable optimizations. Passing the carry down as a value allow for more flexibility. Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer Subscribers: igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D29872 llvm-svn: 301775
* [APInt] Replace calls to setBits with more specific calls to setBitsFrom and ↵Craig Topper2017-04-301-3/+3
| | | | | | setLowBits where possible. llvm-svn: 301768
* [X86] Clear KnownBits instead of reconstructing it. NFCCraig Topper2017-04-301-1/+1
| | | | llvm-svn: 301767
* [globalisel][tablegen] Compute available feature bits correctly.Daniel Sanders2017-04-295-24/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Predicate<> now has a field to indicate how often it must be recomputed. Currently, there are two frequencies, per-module (RecomputePerFunction==0) and per-function (RecomputePerFunction==1). Per-function predicates are currently recomputed more frequently than necessary since the only predicate in this category is cheap to test. Per-module predicates are now computed in getSubtargetImpl() while per-function predicates are computed in selectImpl(). Tablegen now manages the PredicateBitset internally. It should only be necessary to add the required includes. Also fixed a problem revealed by the test case where constrainSelectedInstRegOperands() would attempt to tie operands that BuildMI had already tied. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32491 llvm-svn: 301750
* TargetLowering: Add finalizeLowering() function; NFCMatthias Braun2017-04-282-8/+14
| | | | | | | | | | | | | | | | | Adds a new method finalizeLowering to TargetLoweringBase. This is in preparation for an upcoming commit. This function is meant for target specific adjustments to MachineFrameInfo or register reservations. Move the freezeRegisters() and the hasCopyImplyingStackAdjustment() handling into the new function to prove the concept. As an added bonus GlobalISel no longer missed the hasCopyImplyingStackAdjustment() handling with this. Differential Revision: https://reviews.llvm.org/D32621 llvm-svn: 301679
* Use Argument::hasAttribute and AttributeList::ReturnIndex moreReid Kleckner2017-04-281-9/+6
| | | | | | | | | | | This eliminates many extra 'Idx' induction variables in loops over arguments in CodeGen/ and Target/. It also reduces the number of places where we assume that ReturnIndex is 0 and that we should add one to argument numbers to get the corresponding attribute list index. NFC llvm-svn: 301666
* Clean up DIExpression::prependDIExpr a little. (NFC)Adrian Prantl2017-04-281-4/+3
| | | | llvm-svn: 301662
* Move variable local to where ita used. NFCI.Simon Pilgrim2017-04-281-1/+1
| | | | llvm-svn: 301646
* [DebugInfo][X86] Improve X86 Optimize LEAs handling of debug values.Andrew Ng2017-04-281-7/+48
| | | | | | | | | | | | | | | This is a follow up to the fix in r298360 to improve the handling of debug values when redundant LEAs are removed. The fix in r298360 effectively discarded the debug values. This patch now attempts to preserve the debug values by using the DWARF DW_OP_stack_value operation via prependDIExpr. Moved functions appendOffset and prependDIExpr from Local.cpp to DebugInfoMetadata.cpp and made them available as static member functions of DIExpression. Differential Revision: https://reviews.llvm.org/D31604 llvm-svn: 301630
* [X86][NFC] Refactor RepMovsRepeats in preparation for D32481.Clement Courbet2017-04-281-49/+45
| | | | | | Differential Revision: https://reviews.llvm.org/D32583 llvm-svn: 301628
* [SelectionDAG] Use KnownBits struct in DAG's computeKnownBits and ↵Craig Topper2017-04-284-37/+36
| | | | | | | | | | | | simplifyDemandedBits This patch replaces the separate APInts for KnownZero/KnownOne with a single KnownBits struct. This is similar to what was done to ValueTracking's version recently. This is largely a mechanical transformation from KnownZero to Known.Zero. Differential Revision: https://reviews.llvm.org/D32569 llvm-svn: 301620
* [SelectionDAG] Use various APInt methods to reduce temporary APInt creationCraig Topper2017-04-281-1/+1
| | | | | | This patch uses various APInt methods to reduce the number of temporary APInts. These were all found while working through converting SelectionDAG's computeKnownBits to also use the KnownBits struct recently added to the ValueTracking version. llvm-svn: 301618
* [APInt] Use inplace shift methods where possible. NFCICraig Topper2017-04-281-6/+5
| | | | llvm-svn: 301612
* [GlobalISel][X86] handle not symmetric G_COPYIgor Breger2017-04-271-2/+13
| | | | | | | | | | | | | | Summary: handle not symmetric G_COPY Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32420 llvm-svn: 301523
* [CodeGen][NFC] Rename 'Src' to 'Val'.Clement Courbet2017-04-271-7/+7
| | | | | | | | | 'Src' looks like it was borrowed from memcpy, 'Val' makes more sense for memset and is consistent with naming within the function. Differential Revision: https://reviews.llvm.org/D32580 llvm-svn: 301521
* [X86] Add missing mayLoad/mayStore attributes to some X86 instructions ↵Ayman Musa2017-04-261-4/+6
| | | | | | | | | | (Continue) Complete the patch committed in rL300190. Differential Revision: https://reviews.llvm.org/D32287 llvm-svn: 301393
* PR31007 and PR27884 will be closed: a possibility to compile constants like ↵Andrew V. Tischenko2017-04-261-0/+2
| | | | | | 0bH is now supported in MS asm. llvm-svn: 301390
* [X86][SSE2] Fix asm string for movq (Move Quadword) instruction.Ayman Musa2017-04-261-11/+11
| | | | | | | | Replace "mov{d|q}" with "movq". Differential Revision: https://reviews.llvm.org/D32220 llvm-svn: 301386
* [SelectionDAG] Added getBuildVector(ArrayRef<SDUse>) helper.Simon Pilgrim2017-04-251-4/+4
| | | | llvm-svn: 301322
* Move value type list from TargetRegisterClass to TargetRegisterInfoKrzysztof Parzyszek2017-04-242-7/+9
| | | | | | Differential Revision: https://reviews.llvm.org/D31937 llvm-svn: 301234
* Revert r301231: Accidentally committed stale filesKrzysztof Parzyszek2017-04-242-9/+7
| | | | | | I forgot to commit local changes before commit. llvm-svn: 301232
* Move value type list from TargetRegisterClass to TargetRegisterInfoKrzysztof Parzyszek2017-04-242-7/+9
| | | | | | Differential Revision: https://reviews.llvm.org/D31937 llvm-svn: 301231
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-244-28/+49
| | | | | | | | | | | | | | | 1. RegisterClass::getSize() is split into two functions: - TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const; - TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const; 2. RegisterClass::getAlignment() is replaced by: - TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const; This will allow making those values depend on subtarget features in the future. Differential Revision: https://reviews.llvm.org/D31783 llvm-svn: 301221
* X86RegisterInfo: eliminateFrameIndex: Avoid code duplication; NFCMatthias Braun2017-04-243-34/+24
| | | | | | | | | | | | | | | | | Re-Commit of r300922 and r300923 with less aggressive assert (see discussion at the end of https://reviews.llvm.org/D32205) X86RegisterInfo::eliminateFrameIndex() and X86FrameLowering::getFrameIndexReference() both had logic to compute the base register. This consolidates the code. Also use MachineInstr::isReturn instead of manually enumerating tail call instructions (return instructions were not included in the previous list because they never reference frame indexes). Differential Revision: https://reviews.llvm.org/D32206 llvm-svn: 301211
* [GlobalISel][X86] Lower FormalArgument/Ret using ↵Igor Breger2017-04-242-22/+11
| | | | | | | | | | | | | | | | G_MERGE_VALUES/G_UNMERGE_VALUES. Summary: [GlobalISel][X86] Lower FormalArgument/Ret using G_MERGE_VALUES/G_UNMERGE_VALUES. Reviewers: zvi, t.p.northover, guyblank Reviewed By: t.p.northover Subscribers: dberris, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32288 llvm-svn: 301194
* [X86][SSE] Add scheduler class support for SSE42 (PCMPGT) instructionsSimon Pilgrim2017-04-231-6/+10
| | | | llvm-svn: 301142
* Revert "[APInt] Fix a few places that use APInt::getRawData to operate ↵Renato Golin2017-04-231-5/+6
| | | | | | | | | | | | | | | | within the normal API." This reverts commit r301105, 4, 3 and 1, as a follow up of the previous revert, which broke even more bots. For reference: Revert "[APInt] Use operator<<= where possible. NFC" Revert "[APInt] Use operator<<= instead of shl where possible. NFC" Revert "[APInt] Use ashInPlace where possible." PR32754. llvm-svn: 301111
* [X86][MPX] Add load & store instructions of bnd values to ↵Ayman Musa2017-04-231-22/+30
| | | | | | | | | | getLoadStoreRegOpcode function. This is needed for a follow up patch that generates the memory folding tables. Differential Revision: https://reviews.llvm.org/D32232 llvm-svn: 301109
* [APInt] Use operator<<= where possible. NFCCraig Topper2017-04-231-2/+2
| | | | llvm-svn: 301104
* [APInt] Use operator<<= instead of shl where possible. NFCCraig Topper2017-04-231-2/+1
| | | | llvm-svn: 301103
* [APInt] Use ashInPlace where possible.Craig Topper2017-04-231-2/+2
| | | | llvm-svn: 301101
* Re-commit r301040 "X86: Don't emit zero-byte functions on Windows"Hans Wennborg2017-04-212-2/+2
| | | | | | | | | In addition to the original commit, tighten the condition for when to pad empty functions to COFF Windows. This avoids running into problems when targeting e.g. Win32 AMDGPU, which caused test failures when this was committed initially. llvm-svn: 301047
* Revert r301040 "X86: Don't emit zero-byte functions on Windows"Hans Wennborg2017-04-212-2/+2
| | | | | | This broke almost all bots. Reverting while fixing. llvm-svn: 301041
* X86: Don't emit zero-byte functions on WindowsHans Wennborg2017-04-212-2/+2
| | | | | | | | | | | | | | | | | | Empty functions can lead to duplicate entries in the Guard CF Function Table of a binary due to multiple functions sharing the same RVA, causing the kernel to refuse to load that binary. We had a terrific bug due to this in Chromium. It turns out we were already doing this for Mach-O in certain situations. This patch expands the code for that in AsmPrinter::EmitFunctionBody() and renames TargetInstrInfo::getNoopForMachoTarget() to simply getNoop() since it seems it was used for not just Mach-O anyway. Differential Revision: https://reviews.llvm.org/D32330 llvm-svn: 301040
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