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* Added X86 Atom latencies to X86InstrMMX.td.Preston Gurd2012-05-114-130/+350
| | | | llvm-svn: 156615
* Implement initial-exec TLS model for 32-bit PIC x86Hans Wennborg2012-05-114-16/+35
| | | | | | | This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong code here (see the update to test/CodeGen/X86/tls-pie.ll). llvm-svn: 156611
* Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),Dan Gohman2012-05-111-0/+3
| | | | | | but it generates int3 on x86 instead of ud2. llvm-svn: 156593
* Added X86 Atom latencies for instructions in X86InstrInfo.td.Preston Gurd2012-05-103-223/+426
| | | | llvm-svn: 156579
* Fix merge-typo and cleanupNadav Rotem2012-05-101-5/+3
| | | | llvm-svn: 156541
* AVX2: Add an additional broadcast idiom.Nadav Rotem2012-05-101-2/+5
| | | | llvm-svn: 156540
* Generate AVX/AVX2 shuffles even when there is a memory op somewhere else in ↵Nadav Rotem2012-05-101-4/+0
| | | | | | | | | | the program. Starting r155461 we are able to select patterns for vbroadcast even when the load op is used by other users. Fix PR11900. llvm-svn: 156539
* Use ptr_rc_tailcall instead of GR32_TC.Jakob Stoklund Olesen2012-05-093-6/+7
| | | | | | | | | The getPointerRegClass() hook will return GR32_TC, or whatever is appropriate for the current function. Patch by Yiannis Tsiouris! llvm-svn: 156459
* s/CSR_Ghc/CSR_NoRegs/Jakob Stoklund Olesen2012-05-082-3/+3
| | | | | | | | | Share the CalleeSavedRegs defs between all calling conventions having no callee-saved registers. Patch by Yiannis Tsiouris! llvm-svn: 156382
* Remove 256-bit AVX non-temporal store intrinsics. Similar was previously ↵Craig Topper2012-05-081-7/+0
| | | | | | done for 128-bit. llvm-svn: 156375
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-073-8/+10
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* Fix a regression from r147481. This combine should only happen if there is aChad Rosier2012-05-071-10/+12
| | | | | | | single use. rdar://11360370 llvm-svn: 156316
* X86: optimization for -(x != 0)Manman Ren2012-05-072-0/+22
| | | | | | | | | | | | | | | | | This patch will optimize -(x != 0) on X86 FROM cmpl $0x01,%edi sbbl %eax,%eax notl %eax TO negl %edi sbbl %eax %eax In order to generate negl, I added patterns in Target/X86/X86InstrCompiler.td: def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>; rdar: 10961709 llvm-svn: 156312
* Fix some issues in the f16c instructions.Craig Topper2012-05-071-11/+9
| | | | llvm-svn: 156287
* Add SSE4A MOVNTSS/MOVNTSD instructions.Craig Topper2012-05-071-0/+14
| | | | llvm-svn: 156281
* Use MVT instead of EVT as the argument to all the shuffle decode functions. ↵Craig Topper2012-05-063-35/+33
| | | | | | Simplify some of the decode functions. llvm-svn: 156268
* Add VPERMQ/VPERMPD to the list of target specific shuffles that can be ↵Craig Topper2012-05-061-0/+6
| | | | | | looked through for DAG combine purposes. llvm-svn: 156266
* Add shuffle decode support for VPERMQ/VPERMPD.Craig Topper2012-05-063-0/+22
| | | | llvm-svn: 156265
* Nuke a few dead remnants of the CBE.Jim Grosbach2012-05-051-17/+0
| | | | llvm-svn: 156241
* Add a new target hook "predictableSelectIsExpensive".Benjamin Kramer2012-05-051-0/+3
| | | | | | | | | | | This will be used to determine whether it's profitable to turn a select into a branch when the branch is likely to be predicted. Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM. I'm not entirely happy with the name of this flag, suggestions welcome ;) llvm-svn: 156233
* Adds Intel Atom scheduling latencies to X86InstrSystem.td.Preston Gurd2012-05-043-139/+272
| | | | llvm-svn: 156194
* Fix some loops to match coding standards. No functional change intended.Craig Topper2012-05-041-6/+8
| | | | llvm-svn: 156159
* Fix up some spacing. No functional change.Craig Topper2012-05-041-6/+6
| | | | llvm-svn: 156158
* Simplify broadcast lowering code. No functional change intended.Craig Topper2012-05-041-17/+7
| | | | llvm-svn: 156157
* Allow v16i16 and v32i8 shuffles to be rewritten as narrower shuffles.Craig Topper2012-05-041-5/+8
| | | | llvm-svn: 156156
* Simplify shuffle narrowing code a bit. No functional change intended.Craig Topper2012-05-041-22/+16
| | | | llvm-svn: 156154
* Remove the SubRegClasses field from RegisterClass descriptions.Jakob Stoklund Olesen2012-05-041-78/+19
| | | | | | This information in now computed by TableGen. llvm-svn: 156152
* Use 'unsigned' instead of 'int' in a few places dealing with counts of ↵Craig Topper2012-05-031-3/+3
| | | | | | vector elements. llvm-svn: 156060
* Fix 256-bit vpshuflw and vpshufhw immediate encoding to handle undefs in the ↵Craig Topper2012-05-032-21/+36
| | | | | | lower half correctly. Missed in r155982. llvm-svn: 156059
* For Intel Atom, use ILP scheduling always, instead of ILP for 64 bitPreston Gurd2012-05-021-4/+4
| | | | | | | and Hybrid for 32 bit, since benchmarks show ILP scheduling is better most of the time. llvm-svn: 156028
* Change the Intel Atom detection code to recognizePreston Gurd2012-05-021-1/+2
| | | | | | Lincroft and Medfield. llvm-svn: 156025
* This patch continues the work of adding instruction latencies for X86 Atom,Preston Gurd2012-05-024-68/+171
| | | | | | by providing the latencies for the instructions in X86InstrFPStack.td. llvm-svn: 155996
* Revert r155853Manman Ren2012-05-021-16/+0
| | | | | | | | The commit is intended to fix rdar://10961709. But it is the root cause of PR12720. Revert it for now. llvm-svn: 155992
* Add support for selecting AVX2 vpshuflw and vpshufhw. Add decoding support ↵Craig Topper2012-05-024-36/+90
| | | | | | for AsmPrinter. llvm-svn: 155982
* Remove unneeded break.Jakub Staszak2012-05-011-1/+0
| | | | llvm-svn: 155959
* Remove trailing spaces.Jakub Staszak2012-05-011-43/+43
| | | | llvm-svn: 155956
* This patch marks the X86 floating point stack registers ST0-ST7 as reservedPreston Gurd2012-05-011-0/+10
| | | | | | | | | in order to avoid assertion failures in the register scavenger. The assertion failures were “Bad machine code: Using an undefined physical register” and “Bad machine code: MBB exits via unconditional fall-through but its successor differs from its CFG successor!”. llvm-svn: 155930
* X86: optimization for max-like structManman Ren2012-05-011-0/+40
| | | | | | | | | | | | | | | | | | | | | | | This patch will optimize the following cases on X86 (a > b) ? (a-b) : 0 (a >= b) ? (a-b) : 0 (b < a) ? (a-b) : 0 (b <= a) ? (a-b) : 0 FROM movl %edi, %ecx subl %esi, %ecx cmpl %edi, %esi movl $0, %eax cmovll %ecx, %eax TO xorl %eax, %eax subl %esi, %edi cmovll %eax, %edi movl %edi, %eax rdar: 10734411 llvm-svn: 155919
* X86: Use StackRegister instead of FrameRegister in getFrameIndexReference ↵Alexey Samsonov2012-05-012-0/+14
| | | | | | (to generate debug info for local variables) if stack needs realignment llvm-svn: 155917
* Change the PassManager from a reference to a pointer.Bill Wendling2012-05-011-6/+6
| | | | | | | | | The TargetPassManager's default constructor wants to initialize the PassManager to 'null'. But it's illegal to bind a null reference to a null l-value. Make the ivar a pointer instead. PR12468 llvm-svn: 155902
* Allow BMI, AES, F16C, POPCNT, FMA3, and CLMUL to be detected on AMD processors.Craig Topper2012-05-011-9/+9
| | | | llvm-svn: 155899
* Make XOP and FMA4 require SSE4A to match GCC behavior. Use this to simplify ↵Craig Topper2012-05-011-9/+8
| | | | | | Bulldozer feature list. llvm-svn: 155897
* Attempt to handle MRMInitReg in emitVEXOpcodePrefix. Hopefully fixes PR12711.Craig Topper2012-05-011-1/+12
| | | | llvm-svn: 155896
* Make XOP imply AVX as its needed to legalize the registers types.Craig Topper2012-05-011-1/+2
| | | | llvm-svn: 155891
* Remove HasSSE2 from AES and CLMUL predicates. It's now implied by the HasAES ↵Craig Topper2012-05-011-3/+3
| | | | | | and HasCLMUL predicates. llvm-svn: 155890
* Make CLMUL and AES imply SSE2 since its needed to legalize the type.Craig Topper2012-05-011-2/+4
| | | | llvm-svn: 155888
* Enable AVX and FMA4 for AMD Bulldozer processors.Craig Topper2012-05-011-5/+5
| | | | llvm-svn: 155885
* X86: optimization for -(x != 0)Manman Ren2012-04-301-0/+16
| | | | | | | | | | | | | This patch will optimize -(x != 0) on X86 FROM cmpl $0x01,%edi sbbl %eax,%eax notl %eax TO negl %edi sbbl %eax %eax llvm-svn: 155853
* Tidy up. No functional change intended.Chad Rosier2012-04-301-8/+7
| | | | llvm-svn: 155832
* Fix fastcc structure return with fast-isel on x86-32Derek Schuff2012-04-301-0/+2
| | | | | | | | | | | | | | On x86-32, structure return via sret lets the callee pop the hidden pointer argument off the stack, which the caller then re-pushes. However if the calling convention is fastcc, then a register is used instead, and the caller should not adjust the stack. This is implemented with a check of IsTailCallConvention X86TargetLowering::LowerCall but is now checked properly in X86FastISel::DoSelectCall. (this time, actually commit what was reviewed!) llvm-svn: 155825
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