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* [X86] Fix disassembling of EVEX instructions to stop accidentally decoding ↵Craig Topper2017-10-214-118/+44
| | | | | | | | | | | | the SIB index register as an XMM/YMM/ZMM register. This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB. This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type. This fixes PR32807. llvm-svn: 316273
* [X86] Do not generate __multi3 for mul i128 on X86Craig Topper2017-10-211-0/+1
| | | | | | | | | | | | | | | | Summary: __multi3 is not available on x86 (32-bit). Setting lib call name for MULI_128 to nullptr forces DAGTypeLegalizer::ExpandIntRes_MUL to generate instructions for 128-bit multiply instead of a call to an undefined function. This fixes PR20871 though it may be worth looking at why licm and indvars combine to generate 65-bit multiplies in that test. Patch by Riyaz V Puthiyapurayil Reviewers: craig.topper, schweitz Reviewed By: craig.topper, schweitz Subscribers: RKSimon, llvm-commits Differential Revision: https://reviews.llvm.org/D38668 llvm-svn: 316254
* [X86][SSE] getTargetShuffleMask - check shuffle input value types. NFCI.Simon Pilgrim2017-10-201-0/+46
| | | | | | To help identify shuffle combine issues llvm-svn: 316222
* Make x86 __ehhandler comdat if parent function isDave Lee2017-10-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change comes from using lld for i686-windows-msvc. Before this change, lld emits an error of: error: relocation against symbol in discarded section: .xdata It's possible that this could be addressed in lld, but I think this change is reasonable on its own. At a high level, this is being generated: A (.text comdat) -> B (.text) -> C (.xdata comdat) Where A is a C++ inline function, which references B, an exception handler thunk, which references C, the exception handling info. With this structure, lld will error when applying relocations to B if the C it references has been discarded (some other C has been selected). This change checks if A is comdat, and if so places the exception registration thunk (B) in the comdata group of A (and B). It appears that MSVC makes the __ehhandler function comdat. Is it possible that duplicate thunks are being emitted into the final binary with other linkers, or are they stripping the unused thunks? Reviewers: rnk, majnemer, compnerd, smeenai Reviewed By: rnk, compnerd Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38940 llvm-svn: 316219
* [X86] Remove LowerEXTRACT_SUBVECTOR handler. All EXTRACT_SUBVECTORs are ↵Craig Topper2017-10-191-26/+0
| | | | | | marked as legal. llvm-svn: 316182
* [X86] Replace custom scalar integer absolute matching with ISD::ABS lowering.Simon Pilgrim2017-10-191-36/+21
| | | | | | | | | | | | x86 has its own copy of integer absolute pattern matching to combine directly to a SUB+CMOV. This patch removes the x86 combine and adds custom lowering support for ISD::ABS instead, allowing us to use the DAGCombiner version. Additional test cases are already covered by iabs.ll (rL315706 and rL315711). Differential Revision: https://reviews.llvm.org/D38895 llvm-svn: 316162
* [AVX512][AVX2]Cost calculation for interleave load/store patterns ↵Michael Zuckerman2017-10-181-7/+43
| | | | | | | | | | | | | | | | | | | {v8i8,v16i8,v32i8,v64i8} This patch adds accurate instructions cost. The formula presents two cases(stride 3 and stride 4) and calculates the cost according to the VF and stride. Reviewers: 1. delena 2. Farhana 3. zvi 4. dorit 5. Ayal Differential Revision: https://reviews.llvm.org/D38762 Change-Id: If4cfbd4ac0e63694e8144cb78c7fa34850647ff7 llvm-svn: 316072
* Fixing bug issue https://bugs.llvm.org/show_bug.cgi?id=34978Michael Zuckerman2017-10-181-0/+2
| | | | | Change-Id: I7f13d5bcb181be2860377df7b40e1579a8ad4add llvm-svn: 316067
* Fix `FaultMaps` crash when the out streamer is reusedYichao Yu2017-10-171-0/+1
| | | | | | | | | | | | | | | | | | | Summary: Make sure the map is cleared before processing a new module. Similar to what is done on `StackMaps`. This issue is similar to D38588, though this time for FaultMaps (on x86) rather than ARM/AArch64. Other than possible mixing of information between modules, the crash is caused by the pointers values in the map that was allocated by the bump pointer allocator that is unwinded when emitting the next file. This issue has been around since 3.8. This issue is likely much harder to write a test for since AFAICT it requires emitting something much more compilcated (and possibly real code) instead of just some random bytes. Reviewers: skatkov, sanjoy Reviewed By: skatkov, sanjoy Subscribers: sanjoy, aemerson, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D38924 llvm-svn: 315990
* [X86][SKL] Updated scheduling information for the SkylakeClient targetGadi Haber2017-10-171-3072/+3271
| | | | | | | | | | | | | | Updated the scheduling information for the SkylakeClient target with the following changes: 1. regrouped the instructions after adding load and store latencies. 2. regrouped the instructions after adding identified missing ports in several groups. The changes were made after revisiting the latencies impact of all the load and store uOps. Reviewers: zvi, RKSimon, craig.topper Differential Revision: https://reviews.llvm.org/D38727 Change-Id: I778a308cc11e490e8fa5e27e2047412a1dca029f llvm-svn: 315978
* [X86] Fix typo in comment. NFCCraig Topper2017-10-171-1/+1
| | | | llvm-svn: 315969
* Add iterator range MachineRegisterInfo::liveins(), adopt users, NFCKrzysztof Parzyszek2017-10-162-6/+5
| | | | llvm-svn: 315927
* Fix or vs || typo.Simon Pilgrim2017-10-161-1/+1
| | | | llvm-svn: 315903
* This patch is a result of D37262: The issues with X86 prefixes. It closes ↵Andrew V. Tischenko2017-10-169-171/+264
| | | | | | PR7709, PR17697, PR19251, PR32809 and PR21640. There could be other bugs closed by this patch. llvm-svn: 315899
* [X86] Remove the SlowBTMem feature flag entirelyCraig Topper2017-10-154-66/+31
| | | | | | Turns out we have no patterns on the instructions that were using this feature flag for other reasons. These instructions are slow on all modern CPUs so it seems unlikely that we will spend any effort supporting these instructions going forward. So we might as well just kill of the feature flag and just fix up the comments. llvm-svn: 315862
* [AVX512] Don't mark EXTLOAD as legal with AVX512. Continue using custom ↵Craig Topper2017-10-152-59/+15
| | | | | | | | | | | | | | | | | | | lowering. Summary: This was impeding our ability to combine the extending shuffles with other shuffles as you can see from the test changes. There's one special case that needed to be added to use VZEXT directly for v8i8->v8i64 since the custom lowering requires v64i8. Reviewers: RKSimon, zvi, delena Reviewed By: delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38714 llvm-svn: 315860
* [X86] Add FeatureSlowBTMem to Haswell, Broadwell, Skylake, Cannonlake, and ↵Craig Topper2017-10-151-6/+13
| | | | | | | | | | | | | | | | Knights Landing CPUs. Summary: I see nothing in Agner Fog's tables to indicate that this improved between Ivy Bridge and Haswell. It's also set for all Atom CPUs so I assume KNL should have it too. Reviewers: RKSimon, zvi, gadi.haber Reviewed By: gadi.haber Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38890 llvm-svn: 315859
* Reverting r315590; it did not include changes for llvm-tblgen, which is ↵Aaron Ballman2017-10-152-2/+2
| | | | | | | | causing link errors for several people. Error LNK2019 unresolved external symbol "public: void __cdecl `anonymous namespace'::MatchableInfo::dump(void)const " (?dump@MatchableInfo@?A0xf4f1c304@@QEBAXXZ) referenced in function "public: void __cdecl `anonymous namespace'::AsmMatcherEmitter::run(class llvm::raw_ostream &)" (?run@AsmMatcherEmitter@?A0xf4f1c304@@QEAAXAEAVraw_ostream@llvm@@@Z) llvm-tblgen D:\llvm\2017\utils\TableGen\AsmMatcherEmitter.obj 1 llvm-svn: 315854
* [X86] Ignore DBG instructions in X86CmovConversion optimization to resolve ↵Amjad Aboud2017-10-151-0/+31
| | | | | | | | PR34565 Differential Revision: https://reviews.llvm.org/D38359 llvm-svn: 315851
* [X86] Lower vselect with constant condition to vector_shuffle even with ↵Craig Topper2017-10-151-5/+5
| | | | | | | | | | | | | | | | | | | AVX512 instructions. Summary: It's better to use our shuffle lowering code to handle these than loading an immediate into a k-register. It really feels like this should be a DAG combine optimization rather than a lowering operation, but that's a problem for another day. Reviewers: RKSimon, delena, zvi Reviewed By: delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38932 llvm-svn: 315849
* [X86][SSE] Don't attempt to reduce the imul vector width of odd sized ↵Simon Pilgrim2017-10-141-1/+4
| | | | | | vectors (PR34947) llvm-svn: 315825
* Pull out repeated calls to VT.getVectorNumElements(). NFCI.Simon Pilgrim2017-10-141-10/+11
| | | | llvm-svn: 315818
* Use DAG::getBitcast() helper. NFCI.Simon Pilgrim2017-10-141-4/+4
| | | | llvm-svn: 315815
* [X86][SSE] Support combining AND(EXTRACT(SHUF(X)), C) -> EXTRACT(SHUF(X))Simon Pilgrim2017-10-141-0/+39
| | | | | | | | If we are applying a byte mask to a value extracted from a shuffle, see if we can combine the mask into shuffle. Fixes the last issue with PR22415 llvm-svn: 315807
* [X86] Add patterns for vzmovl+cvtpd2dq/cvttpd2dq with a load.Craig Topper2017-10-142-1/+19
| | | | llvm-svn: 315802
* [X86] Add AVX512 versions of VCVTPD2PS to load folding tables.Craig Topper2017-10-141-0/+3
| | | | llvm-svn: 315801
* [X86] Add patterns for vzmovl+cvtpd2ps with a load.Craig Topper2017-10-142-12/+24
| | | | llvm-svn: 315800
* [X86] Remove some patterns for bitcasted alignednonedtemporalloads.Craig Topper2017-10-141-18/+0
| | | | | | These select the same instruction as the non-bitcasted pattern. So this provides no additional value. llvm-svn: 315799
* [X86] Remove unnecessary bitconverts as the root of patterns for zero ↵Craig Topper2017-10-141-4/+4
| | | | | | | | extended VCVTPD2UDQZ128rr and VCVTTPD2UDQZ128rr. We don't need a bitconvert as a root pattern in these cases. The types in the other parts of the pattern are sufficient to express the behavior of these instructions. llvm-svn: 315798
* [X86] Add additional patterns for folding loads with 128-bit VCVTDQ2PD and ↵Craig Topper2017-10-141-0/+10
| | | | | | | | | | VCVTUDQ2PD. This matches the patterns we have for the SSE/AVX version. This is a prerequisite for D38714. llvm-svn: 315797
* [X86] Add AVX512 flavors of VCVTDQ2PD plus VCVTUDQ2PD to the load folding ↵Craig Topper2017-10-141-0/+6
| | | | | | tables. llvm-svn: 315796
* [X86] Remove TB_NO_REVERSE from VCVTDQ2PDYrr and VCVTPS2PDYrr in the load ↵Craig Topper2017-10-141-2/+2
| | | | | | | | folding tables. I believe these were added incorrectly under the belief that the load size was smaller than the input register size, but that's not true. llvm-svn: 315795
* [X86] Add an additional isel pattern to CVTDQ2PDrm/VCVTDQ2PDrm to enable ↵Craig Topper2017-10-141-2/+6
| | | | | | | | load folding without the peephole pass. This pattern is already used in AVX512VL version of these instructions. Though AVX512VL version is missing other patterns. llvm-svn: 315794
* [X86] Use X86ISD::VBROADCAST in place of v2f64 X86ISD::MOVDDUP when AVX2 is ↵Craig Topper2017-10-133-17/+27
| | | | | | | | | | | | | | | | available This is particularly important for AVX512VL where we are better able to recognize the VBROADCAST loads to fold with other operations. For AVX512VL we now use X86ISD::VBROADCAST for all of the patterns and remove the 128-bit X86ISD::VMOVDDUP. We may be able to use this for AVX1 as well which would allow us to remove more isel patterns. I also had to add X86ISD::VBROADCAST as a node to call combineShuffle for so that we treat it similar to X86ISD::MOVDDUP. Differential Revision: https://reviews.llvm.org/D38836 llvm-svn: 315768
* [globalisel][tablegen] Add support for fpimm and import of APInt/APFloat ↵Daniel Sanders2017-10-131-8/+8
| | | | | | | | | | | | | | | | | | | | | | based ImmLeaf. Summary: There's only a tablegen testcase for IntImmLeaf and not a CodeGen one because the relevant rules are rejected for other reasons at the moment. On AArch64, it's because there's an SDNodeXForm attached to the operand. On X86, it's because the rule either emits multiple instructions or has another predicate using PatFrag which cannot easily be supported at the same time. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36569 llvm-svn: 315761
* [X86] Add initial skeleton support for knm cpuCraig Topper2017-10-131-5/+16
| | | | | | | | This adds Intel's Knights Mill CPU to valid CPU names for the backend. For now its an alias of "knl", but ultimately we need to support AVX5124FMAPS and AVX5124VNNIW instruction sets for it. Differential Revision: https://reviews.llvm.org/D38811 llvm-svn: 315722
* [X86] Fix some inconsistent formatting in the processor feature lists.Craig Topper2017-10-131-4/+4
| | | | llvm-svn: 315696
* [X86] Add ProcIntelBDW to BroadwellProc class not BDWFeatures class.Craig Topper2017-10-131-4/+5
| | | | | | This isn't a property we want inherited. llvm-svn: 315695
* [X86] Stop creating CMOV nodes with a second MVT::Glue resultCraig Topper2017-10-131-24/+9
| | | | | | | | | | | | | | Summary: We seem to inconsistently create CMOV nodes some with a Glue result and some without. But I can't find any cases that use the Glue result. So I've tried to remove all the place that did this. Reviewers: RKSimon, spatel, zvi Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38664 llvm-svn: 315686
* [X86] Remove patterns that select unmasked vbroadcastf2x32/vbroadcasti2x32. ↵Craig Topper2017-10-131-8/+20
| | | | | | | | Prefer vbroadcastsd/vpbroadcastq instead. There's no advantage to using these instructions when they aren't masked. This enables some additional execution domain switching without needing to update the table. llvm-svn: 315674
* Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine"Matthias Braun2017-10-122-2/+2
| | | | | | | | | | Reverting to investigate layering effects of MCJIT not linking libCodeGen but using TargetMachine::getNameWithPrefix() breaking the lldb bots. This reverts commit r315633. llvm-svn: 315637
* TargetMachine: Merge TargetMachine and LLVMTargetMachineMatthias Braun2017-10-122-2/+2
| | | | | | | | | | | | | | | Merge LLVMTargetMachine into TargetMachine. - There is no in-tree target anymore that just implements TargetMachine but not LLVMTargetMachine. - It should still be possible to stub out all the various functions in case a target does not want to use lib/CodeGen - This simplifies the code and avoids methods ending up in the wrong interface. Differential Revision: https://reviews.llvm.org/D38489 llvm-svn: 315633
* [X86] Add CLWB intrinsic. llvm partCraig Topper2017-10-121-2/+2
| | | | llvm-svn: 315613
* [codeview] Don't emit FPO data in funclet prologuesReid Kleckner2017-10-122-6/+3
| | | | | | Attempt 3 to work around bugs in FPO data with funclets. llvm-svn: 315600
* [dump] Remove NDEBUG from test to enable dump methods [NFC]Don Hinton2017-10-122-2/+2
| | | | | | | | | | | | | | | Summary: Add LLVM_FORCE_ENABLE_DUMP cmake option, and use it along with LLVM_ENABLE_ASSERTIONS to set LLVM_ENABLE_DUMP. Remove NDEBUG and only use LLVM_ENABLE_DUMP to enable dump methods. Move definition of LLVM_ENABLE_DUMP from config.h to llvm-config.h so it'll be picked up by public headers. Differential Revision: https://reviews.llvm.org/D38406 llvm-svn: 315590
* [x86] replace isEqualTo with == for efficiencySanjay Patel2017-10-121-4/+4
| | | | | | | This is a follow-up suggested in D37534. Patch by Yulia Koval. llvm-svn: 315589
* [X86][SSE] Pull out repeated INSERT_VECTOR_ELT code from LowerBUILD_VECTOR ↵Simon Pilgrim2017-10-121-57/+51
| | | | | | v16i8/v8i16 insertion. NFCI. llvm-svn: 315587
* Speculative build fix 2Reid Kleckner2017-10-121-1/+1
| | | | llvm-svn: 315542
* Revert r307036 because of PR34919.Wei Mi2017-10-121-13/+0
| | | | llvm-svn: 315540
* Speculative build fix, apparently I built llc without my patch applied to ↵Reid Kleckner2017-10-121-1/+1
| | | | | | test it llvm-svn: 315539
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