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* [WinEH] Move WinEHFuncInfo from MachineModuleInfo to MachineFunctionReid Kleckner2015-11-173-98/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Now that there is a one-to-one mapping from MachineFunction to WinEHFuncInfo, we don't need to use a DenseMap to select the right WinEHFuncInfo for the current funclet. The main challenge here is that X86WinEHStatePass is an IR pass that doesn't have access to the MachineFunction. I gave it its own WinEHFuncInfo object that it uses to calculate state numbers, which it then throws away. As long as nobody creates or removes EH pads between this pass and SDAG construction, we will get the same state numbers. The other thing X86WinEHStatePass does is to mark the EH registration node. Instead of communicating which alloca was the registration through WinEHFuncInfo, I added the llvm.x86.seh.ehregnode intrinsic. This intrinsic generates no code and simply marks the alloca in use. Reviewers: JCTremoulet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14668 llvm-svn: 253378
* [Assembler] Make fatal assembler errors non-fatalOliver Stannard2015-11-171-3/+4
| | | | | | | | | | | | | | Currently, if the assembler encounters an error after parsing (such as an out-of-range fixup), it reports this as a fatal error, and so stops after the first error. However, for most of these there is an obvious way to recover after emitting the error, such as emitting the fixup with a value of zero. This means that we can report on all of the errors in a file, not just the first one. MCContext::reportError records the fact that an error was encountered, so we won't actually emit an object file with the incorrect contents. Differential Revision: http://reviews.llvm.org/D14717 llvm-svn: 253328
* [X86][SSE] Merged BLEND shuffle decode comments. NFC.Simon Pilgrim2015-11-161-48/+8
| | | | | | Now that we can recognise different vector sizes. llvm-svn: 253268
* [X86][SSE] Merged ALIGNR/SLLDQ/SRLDQ shuffle decode comments. NFC.Simon Pilgrim2015-11-161-30/+4
| | | | | | Now that we can recognise different vector sizes - will make future AVX512 additions easier. llvm-svn: 253266
* [X86][SSE] Merged SHUF/PERM shuffle decode comments. NFC.Simon Pilgrim2015-11-161-79/+14
| | | | | | Now that we can recognise different vector sizes - will make future AVX512 additions easier. llvm-svn: 253260
* [X86][SSE] Merged UNPCK shuffle decode comments. NFC.Simon Pilgrim2015-11-161-193/+75
| | | | | | Now that we can recognise different vector sizes - will make future AVX512 additions easier. llvm-svn: 253258
* [WinEH] Don't let UnwindHelp alias the return addressReid Kleckner2015-11-161-6/+6
| | | | | | | | | | | On top of that, don't bother allocating and initializing UnwindHelp if we don't have any funclets. Currently we always use RBP as our frame pointer when funclets are present, so this change makes it impossible to come here without any fixed stack objects. Fixes PR25533. llvm-svn: 253245
* Use the subtarget reference that we already haveReid Kleckner2015-11-161-2/+1
| | | | llvm-svn: 253244
* AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP ↵Igor Breger2015-11-164-107/+108
| | | | | | | | instructions. Differential Revision: http://reviews.llvm.org/D14322 llvm-svn: 253185
* [X86][SSE] Tidyup with implicit SDValue bool check. NFC.Simon Pilgrim2015-11-151-8/+5
| | | | llvm-svn: 253171
* Revert r253160.Igor Breger2015-11-154-108/+107
| | | | | | It broke layering violation. Reproducible with BUILD_SHARED_LIBS=ON. llvm-svn: 253163
* AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP ↵Igor Breger2015-11-154-107/+108
| | | | | | | | instructions. Differential Revision: http://reviews.llvm.org/D14322 llvm-svn: 253160
* Reduce the size of MCRelaxableFragment.Akira Hatanaka2015-11-143-17/+20
| | | | | | | | | | | | | | | | | | | | | | MCRelaxableFragment previously kept a copy of MCSubtargetInfo and MCInst to enable re-encoding the MCInst later during relaxation. A copy of MCSubtargetInfo (instead of a reference or pointer) was needed because the feature bits could be modified by the parser. This commit replaces the MCSubtargetInfo copy in MCRelaxableFragment with a constant reference to MCSubtargetInfo. The copies of MCSubtargetInfo are kept in MCContext, and the target parsers are now responsible for asking MCContext to provide a copy whenever the feature bits of MCSubtargetInfo have to be toggled. With this patch, I saw a 4% reduction in peak memory usage when I compiled verify-uselistorder.lto.bc using llc. rdar://problem/21736951 Differential Revision: http://reviews.llvm.org/D14346 llvm-svn: 253127
* [MCTargetAsmParser] Move the member varialbes that referenceAkira Hatanaka2015-11-141-9/+8
| | | | | | | | | | MCSubtargetInfo in the subclasses into MCTargetAsmParser and define a member function getSTI. This is done in preparation for making changes to shrink the size of MCRelaxableFragment. (see http://reviews.llvm.org/D14346). llvm-svn: 253124
* Add MMX to the 3dnow enum and propagate changes around. This makesEric Christopher2015-11-143-13/+8
| | | | | | it somewhat more consistent with how the feature is used. llvm-svn: 253122
* [WinEH] Fix ESP management with 32-bit __CxxFrameHandler3Reid Kleckner2015-11-132-1/+17
| | | | | | | | | | | | | | | The C++ EH personality automatically restores ESP from the C++ EH registration node after a catchret. I mistakenly thought it was like SEH, which does not restore ESP. It makes sense for C++ EH to differ from SEH here because SEH does not use funclets for catches, and does not allow catching inside of finally. C++ EH may need to unwind through multiple catch funclets and eventually catchret to some outer funclet. Therefore, the runtime has to keep track of which ESP to use with catchret, rather than having the compiler reload it manually. llvm-svn: 253084
* [X86][SSE] Combine UNPCKL with vector_shuffle into UNPCKH to save one ↵Cong Hou2015-11-131-0/+35
| | | | | | | | | | | | | | | | | | | instruction for sext from v16i8 to v16i16 and v8i16 to v8i32. This patch is enabling combining UNPCKL with vector_shuffle that moves the upper half of a vector into the lower half, into a UNPCKH instruction. For example: t2: v16i8 = vector_shuffle<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u> t1, undef:v16i8 t3: v16i8 = X86ISD::UNPCKL undef:v16i8, t2 will be combined to: t3: v16i8 = X86ISD::UNPCKH undef:v16i8, t1 Differential revision: http://reviews.llvm.org/D14399 llvm-svn: 253067
* [WinEH] Make UnwindHelp a fixed stack object allocated after XMM CSRsReid Kleckner2015-11-133-16/+45
| | | | | | | Now the offset of UnwindHelp in our EH tables and the offset that we store to in the prologue agree. llvm-svn: 253059
* [WinEH] Find root frame correctly in CLR funcletsJoseph Tremoulet2015-11-133-18/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The value that the CoreCLR personality passes to a funclet for the establisher frame may be the root function's frame or may be the parent funclet's (mostly empty) frame in the case of nested funclets. Each funclet stores a pointer to the root frame in its own (mostly empty) frame, as does the root function itself. All frames allocate this slot at the same offset, measured from the post-prolog stack pointer, so that the same sequence can accept any ancestor as an establisher frame parameter value, and so that a single offset can be reported to the GC, which also looks at this slot. This change allocate the slot when processing function entry, and records its frame index on the WinEHFuncInfo object, then inserts the code to set/copy it during prolog emission. Reviewers: majnemer, AndyAyers, pgavlin, rnk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14614 llvm-svn: 252983
* X86-FMA3: Implemented commute transformations FMA*_Int instructions.Vyacheslav Klochkov2015-11-132-124/+212
| | | | | | | | | | It made it possible to apply the memory folding optimization for the 2nd operand of FMA*_Int instructions. Reviewer: Quentin Colombet Differential Revision: http://reviews.llvm.org/D14550 llvm-svn: 252973
* My first/test commit. Removed a trailing whitespace.Vyacheslav Klochkov2015-11-121-1/+1
| | | | llvm-svn: 252940
* [x86] translating "fp" (floating point) instructions from ↵Michael Zuckerman2015-11-122-0/+16
| | | | | | | | | | | {fadd,fdiv,fmul,fsub,fsubr,fdivr} to {faddp,fdivp,fmulp,fsubp,fsubrp,fdivrp} LLVM Missing the following instructions: fadd\fdiv\fmul\fsub\fsubr\fdivr. GAS and MS supporting this instruction and lowering them in to a faddp\fdivp\fmulp\fsubp\fsubrp\fdivrp instructions. Differential Revision: http://reviews.llvm.org/D14217 llvm-svn: 252908
* [TLS on Darwin] use a different mask for tls calls on x86-64.Manman Ren2015-11-124-0/+16
| | | | | | | | | Calls involved in thread-local variable lookup save more registers than normal calls. rdar://problem/23073171 llvm-svn: 252837
* [WinEH] Only generate UnwindHelp slot for MSVCXXJoseph Tremoulet2015-11-111-12/+12
| | | | | | | | | | | | Summary: Other personalities don't use this special frame slot. Reviewers: majnemer, andrew.w.kaylor, rnk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14580 llvm-svn: 252778
* Visibly fail if attempting to encode register AH,BH,CH,DH in a REX-prefixed ↵Douglas Katzman2015-11-111-0/+7
| | | | | | | | | instruction. Differential Revision: http://reviews.llvm.org/D13316 Fixes PR25003 llvm-svn: 252743
* Silencing nine warnings for "enumeral and non-enumeral type in conditional ↵Aaron Ballman2015-11-111-10/+18
| | | | | | expression"; NFC. llvm-svn: 252728
* [X86] Replace LEAs with INC/DEC when profitableMichael Kuperstein2015-11-111-8/+79
| | | | | | | | | If possible and profitable, replace lea %reg, 1(%reg) and lea %reg, -1(%reg) with inc %reg and dec %reg respectively. Patch by: anton.nadolsky@intel.com Differential Revision: http://reviews.llvm.org/D14059 llvm-svn: 252722
* [X86] Fix feature flags on some MMX register instructions that really were ↵Craig Topper2015-11-111-2/+13
| | | | | | introduced with SSE or SSE2. llvm-svn: 252709
* [X86] Remove redundant MMX isel patterns.Craig Topper2015-11-111-4/+0
| | | | llvm-svn: 252708
* [WinEH] Insert the MBB for EH_RESTORE after the catchretReid Kleckner2015-11-101-1/+1
| | | | | | | Inserting it before the target block could be bad, we might already have a fallthrough edge to it. llvm-svn: 252670
* [X86] Do not try to custom-lower sitofp/fptosi in soft-float modeMichael Kuperstein2015-11-101-11/+17
| | | | | | Differential Revision: http://reviews.llvm.org/D14495 llvm-svn: 252621
* AVX512 : Implemented encoding and DAG lowering for VMOVHPS/PD and VMOVLPS/PD ↵Igor Breger2015-11-102-5/+119
| | | | | | | | instructions. Differential Revision: http://reviews.llvm.org/D14492 llvm-svn: 252592
* Remove another variable unused in -Asserts buildDavid Blaikie2015-11-101-2/+2
| | | | llvm-svn: 252582
* Remove some unused variables to clean up the -Werror buildDavid Blaikie2015-11-102-4/+4
| | | | llvm-svn: 252580
* Support for emitting inline stack probesAndy Ayers2015-11-103-30/+320
| | | | | | | | | | | | | | | | | | For CoreCLR on Windows, stack probes must be emitted as inline sequences that probe successive stack pages between the current stack limit and the desired new stack pointer location. This implements support for the inline expansion on x64. For in-body alloca probes, expansion is done during instruction lowering. For prolog probes, a stub call is initially emitted during prolog creation, and expanded after epilog generation, to avoid complications that arise when introducing new machine basic blocks during prolog and epilog creation. Added a new test case, modified an existing one to exclude non-x64 coreclr (for now). Add test case Fix tests llvm-svn: 252578
* [WinEH] Remove isBarrier from instructions that do not returnReid Kleckner2015-11-091-2/+2
| | | | | | Fixes machine verification failures with David's latest EH change. llvm-svn: 252541
* add a SelectionDAG method to check if no common bits are set in two nodes; NFCISanjay Patel2015-11-091-17/+5
| | | | | | | | | | | | | | | This was suggested in: http://reviews.llvm.org/D13956 and is a follow-on to: http://reviews.llvm.org/rL252515 http://reviews.llvm.org/rL252519 This lets us remove logically equivalent/duplicated code from DAGCombiner and X86ISelDAGToDAG. A corresponding function for IR instructions already exists in ValueTracking. llvm-svn: 252539
* [WinEH] Don't emit CATCHRET from visitCatchPadDavid Majnemer2015-11-093-10/+27
| | | | | | | Instead, emit a CATCHPAD node which will get selected to a target specific sequence. llvm-svn: 252528
* [x86] try harder to match bitwise 'or' into an LEASanjay Patel2015-11-091-11/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The motivation for this patch starts with the epic fail example in PR18007: https://llvm.org/bugs/show_bug.cgi?id=18007 ...unfortunately, this patch makes no difference for that case, but it solves some simpler cases. We'll get there some day. :) The current 'or' matching code was using computeKnownBits() via isBaseWithConstantOffset() -> MaskedValueIsZero(), but that's an unnecessarily limited use. We can do more by copying the logic in ValueTracking's haveNoCommonBitsSet(), so we can treat the 'or' as if it was an 'add'. There's a TODO comment here because we should lift the bit-checking logic into a helper function, so it's not duplicated in DAGCombiner. An example of the better LEA matching: leal (%rdi,%rdi), %eax andl $1, %esi orl %esi, %eax Becomes: andl $1, %esi leal (%rsi,%rdi,2), %eax Differential Revision: http://reviews.llvm.org/D13956 llvm-svn: 252515
* [WinEH] Tweak funclet prologue/epilogue insertion to pass verifierReid Kleckner2015-11-091-5/+8
| | | | | | | | | | For some reason we'd never run MachineVerifier on WinEH code, and you explicitly have to ask for it with llc. I added it to a few test cases to get some coverage. Fixes PR25461. llvm-svn: 252512
* [WinEH] Update PHIs of CATCHRET successorsDavid Majnemer2015-11-081-2/+2
| | | | | | | | | | | The TailDuplication machine pass ran across a malformed CFG: a PHI node referred it's predecessor's predecessor instead of it's predecessor. This occurred because we split the edge in X86ISelLowering when we processed the CATCHRET but forgot to do something about the PHI nodes. This fixes PR25444. llvm-svn: 252413
* [WinEH] Update exception pointer registersJoseph Tremoulet2015-11-072-7/+26
| | | | | | | | | | | | | | | | | | | | Summary: The CLR's personality routine passes these in rdx/edx, not rax/eax. Make getExceptionPointerRegister a virtual method parameterized by personality function to allow making this distinction. Similarly make getExceptionSelectorRegister a virtual method parameterized by personality function, for symmetry. Reviewers: pgavlin, majnemer, rnk Subscribers: jyknight, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D14344 llvm-svn: 252383
* [X86] Fold (trunc (i32 (zextload i16))) into vbroadcast.Ahmed Bougacha2015-11-061-0/+6
| | | | | | | | | | | When matching non-LSB-extracting truncating broadcasts, we now insert the necessary SRL. If the scalar resulted from a load, the SRL will be folded into it, creating a narrower, offset, load. However, i16 loads aren't Desirable, so we get i16->i32 zextloads. We already catch i16 aextloads; catch these as well. llvm-svn: 252363
* [X86] SRL non-LSB extracts when folding to truncating broadcasts.Ahmed Bougacha2015-11-061-4/+9
| | | | | | | | | | | | Now that we recognize this, we can support it instead of bailing out. That is, we can fold: (v8i16 (shufflevector (v8i16 (bitcast (v4i32 (build_vector X, Y, ...)))), <1,1,...,1>)) into: (v8i16 (vbroadcast (i16 (trunc (srl Y, 16))))) llvm-svn: 252362
* [X86] Don't fold non-LSB extracts into truncating broadcasts.Ahmed Bougacha2015-11-061-12/+52
| | | | | | | | | | | | | | | We used to incorrectly assume that the offset we're extracting from was a multiple of the element size. So, we'd fold: (v8i16 (shufflevector (v8i16 (bitcast (v4i32 (build_vector X, Y, ...)))), <1,1,...,1>)) into: (v8i16 (vbroadcast (i16 (trunc Y)))) whereas we should have extracted the higher bits from X. Instead, bail out if the assumption doesn't hold. llvm-svn: 252361
* Improved the operands commute transformation for X86-FMA3 instructions.Andrew Kaylor2015-11-063-80/+411
| | | | | | | | | | | | All 3 operands of FMA3 instructions are commutable now. Patch by Slava Klochkov Reviewers: Quentin Colombet(qcolombet), Ahmed Bougacha(ab). Differential Revision: http://reviews.llvm.org/D13269 llvm-svn: 252335
* [WinEH] Mark funclet entries and exits as clobbering all registersReid Kleckner2015-11-061-1/+1
| | | | | | | | | | | | | | | | | Summary: In this implementation, LiveIntervalAnalysis invents a few register masks on basic block boundaries that preserve no registers. The nice thing about this is that it prevents the prologue inserter from thinking it needs to spill all XMM CSRs, because it doesn't see any explicit physreg defs in the MI. Reviewers: MatzeB, qcolombet, JosephTremoulet, majnemer Subscribers: MatzeB, llvm-commits Differential Revision: http://reviews.llvm.org/D14407 llvm-svn: 252318
* [WinEH] Split EH_RESTORE out of CATCHRET for 32-bit EHReid Kleckner2015-11-066-52/+90
| | | | | | | | | | | | | | | | | | | | | | | This adds the EH_RESTORE x86 pseudo instr, which is responsible for restoring the stack pointers: EBP and ESP, and ESI if stack realignment is involved. We only need this on 32-bit x86, because on x64 the runtime restores CSRs for us. Previously we had to keep the CATCHRET instruction around during SEH so that we could convince X86FrameLowering to restore our frame pointers. Now we can split these instructions earlier. This was confusing, because we had a return instruction which wasn't really a return and was ultimately going to be removed by X86FrameLowering. This change also simplifies X86FrameLowering, which really shouldn't be building new MBBs. No observable functional change currently, but with the new register mask stuff in D14407, CATCHRET will become a register allocator barrier, and our existing tests rely on us having reasonable register allocation around SEH. llvm-svn: 252266
* Remove windows line endings introduced by r252177. NFC.Tim Northover2015-11-051-9/+9
| | | | llvm-svn: 252217
* [WinEH] Fix funclet prologues with stack realignmentReid Kleckner2015-11-053-34/+53
| | | | | | | | | | | | | | We already had a test for this for 32-bit SEH catchpads, but those don't actually create funclets. We had a bug that only appeared in funclet prologues, where we would establish EBP and ESI as our FP and BP, and then downstream prologue code would overwrite them. While I was at it, I fixed Win64+funclets+stackrealign. This issue doesn't come up as often there due to the ABI requring 16 byte stack alignment, but now we can rest easy that AVX and WinEH will work well together =P. llvm-svn: 252210
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