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* Revert "make reciprocal estimate code generation more flexible by adding ↵Rafael Espindola2015-05-235-41/+54
| | | | | | | | | | | | command-line options" This reverts commit r238051. It broke some bots: http://lab.llvm.org:8011/builders/llvm-ppc64-linux1/builds/18190 llvm-svn: 238075
* make reciprocal estimate code generation more flexible by adding ↵Sanjay Patel2015-05-225-54/+41
| | | | | | | | | | | | | | | | command-line options This patch adds a class for processing many recip codegen possibilities. The TargetRecip class is intended to handle both command-line options to llc as well as options passed in from a front-end such as clang with the -mrecip option. The x86 backend is updated to use the new functionality. Only -mcpu=btver2 with -ffast-math should see a functional change from this patch. All other CPUs continue to *not* use reciprocal estimates by default with -ffast-math. Differential Revision: http://reviews.llvm.org/D8982 llvm-svn: 238051
* Reapply r238011 with a fix for the trap instruction.Quentin Colombet2015-05-227-110/+249
| | | | | | | | | | | | | | | | | | | The problem was that I slipped a change required for shrink-wrapping, namely I used getFirstTerminator instead of the getLastNonDebugInstr that was here before the refactoring, whereas the surrounding code is not yet patched for that. Original message: [X86] Refactor the prologue emission to prepare for shrink-wrapping. - Add a late pass to expand pseudo instructions (tail call and EH returns). Instead of doing it in the prologue emission. - Factor some static methods in X86FrameLowering to ease code sharing. NFC. Related to <rdar://problem/20821487> llvm-svn: 238035
* Revert "[X86] Fix a variable name for r237977 so that it works with every ↵Tamas Berghammer2015-05-227-250/+111
| | | | | | | | | | | compilers." Revert "[X86] Refactor the prologue emission to prepare for shrink-wrapping." This reverts commit 6b3b93fc8b68a2c806aa992ee4bd3d7f61898d4b. This reverts commit ab0b15dff8539826283a59c2dd700a18a9680e0f. llvm-svn: 238011
* [X86] Fix a variable name for r237977 so that it works with every compilers.Quentin Colombet2015-05-221-3/+3
| | | | llvm-svn: 237980
* [X86] Refactor the prologue emission to prepare for shrink-wrapping.Quentin Colombet2015-05-227-111/+250
| | | | | | | | | | | | - Add a late pass to expand pseudo instructions (tail call and EH returns). Instead of doing it in the prologue emission. - Factor some static methods in X86FrameLowering to ease code sharing. NFC. Related to <rdar://problem/20821487> llvm-svn: 237977
* Move alignment from MCSectionData to MCSection.Rafael Espindola2015-05-213-17/+14
| | | | | | | | | | | | | | | | | | | | | | | | This starts merging MCSection and MCSectionData. There are a few issues with the current split between MCSection and MCSectionData. * It optimizes the the not as important case. We want the production of .o files to be really fast, but the split puts the information used for .o emission in a separate data structure. * The ELF/COFF/MachO hierarchy is not represented in MCSectionData, leading to some ad-hoc ways to represent the various flags. * It makes it harder to remember where each item is. The attached patch starts merging the two by moving the alignment from MCSectionData to MCSection. Most of the patch is actually just dropping 'const', since MCSectionData is mutable, but MCSection was not. llvm-svn: 237936
* AVX-512: Enabled SSE intrinsics on AVX-512.Elena Demikhovsky2015-05-212-14/+33
| | | | | | | | | Predicate UseAVX depricates pattern selection on AVX-512. This predicate is necessary for DAG selection to select EVEX form. But mapping SSE intrinsics to AVX-512 instructions is not ready yet. So I replaced UseAVX with HasAVX for intrinsics patterns. llvm-svn: 237903
* Fixed unused variable warning in non-assert builds from rL237885Simon Pilgrim2015-05-211-2/+1
| | | | llvm-svn: 237889
* [X86][SSE] Improve support for 128-bit vector sign extensionSimon Pilgrim2015-05-211-6/+115
| | | | | | | | | | This patch improves support for sign extension of the lower lanes of vectors of integers by making use of the SSE41 pmovsx* sign extension instructions where possible, and optimizing the sign extension by shifts on pre-SSE41 targets (avoiding the use of i64 arithmetic shifts which require scalarization). It converts SIGN_EXTEND nodes to SIGN_EXTEND_VECTOR_INREG where necessary, that more closely matches the pmovsx* instruction than the default approach of using SIGN_EXTEND_INREG which splits the operation (into an ANY_EXTEND lowered to a shuffle followed by shifts) making instruction matching difficult during lowering. Necessary support for SIGN_EXTEND_VECTOR_INREG has been added to the DAGCombiner. Differential Revision: http://reviews.llvm.org/D9848 llvm-svn: 237885
* [WinEH] Store pointers to the LSDA in the exception registration objectReid Kleckner2015-05-202-13/+88
| | | | | | | We aren't yet emitting the LSDA yet, so this will still fail to assemble. llvm-svn: 237852
* Revert r237828 "[X86] Remove unused node after morphing it from shr to and."Hans Wennborg2015-05-201-1/+0
| | | | | | This caused assertions during DAG combine: PR23601. llvm-svn: 237843
* [X86] Remove unused node after morphing it from shr to and.Benjamin Kramer2015-05-201-0/+1
| | | | | | | | | In some cases it won't get cleaned up properly leading to crashes downstream. PR23353. Based on a patch by Davide Italiano. llvm-svn: 237828
* MC: Update MCAssembler to use MCSymbol, NFCDuncan P. N. Exon Smith2015-05-201-3/+3
| | | | | | Use `MCSymbol` over `MCSymbolData` where both are needed. llvm-svn: 237803
* MC: Use MCSymbol in MachObjectWriter, NFCDuncan P. N. Exon Smith2015-05-201-14/+13
| | | | | | | Replace uses of `MCSymbolData` with `MCSymbol` where both are needed, so we can remove the backpointer. llvm-svn: 237799
* AVX-512: fixed algorithm of building vectors of i1 elementsElena Demikhovsky2015-05-203-65/+134
| | | | | | | | fixed extract-insert i1 element, load i1, zextload i1 should be with "and $1, %reg" to prevent loading garbage. added a bunch of new tests. llvm-svn: 237793
* [X86] Implement the local-exec TLS model for Windows targetsDavid Majnemer2015-05-201-14/+19
| | | | | | | We know that _tls_index is zero for local-exec TLS variables because they are always defined in the executable. llvm-svn: 237772
* MC: Take MCSymbol in MachObjectWriter::getSymbolAddress(), NFCDuncan P. N. Exon Smith2015-05-201-13/+11
| | | | | | | Pass through an `MCSymbol` instead of an `MCSymbolData` so we can get rid of the back pointer. llvm-svn: 237750
* MC: Use MCSymbol in MCAsmLayout::getSymbolOffset(), NFCDuncan P. N. Exon Smith2015-05-191-4/+4
| | | | | | | Continue to canonicalize on MCSymbol instead of MCSymbolData when both are needed. llvm-svn: 237749
* MachineInstr: Remove unused parameter.Matthias Braun2015-05-191-1/+1
| | | | llvm-svn: 237726
* [X86] ABI change for x86-32: pass 3 vector arguments in-register instead of ↵Michael Kuperstein2015-05-191-27/+62
| | | | | | | | | | | | | | | | 4, except on Darwin. This changes the ABI used on 32-bit x86 for passing vector arguments. Historically, clang passes the first 4 vector arguments in-register, and additional vector arguments on the stack, regardless of platform. That is different from the behavior of gcc, icc, and msvc, all of which pass only the first 3 arguments in-register. The 3-register convention is documented, unofficially, in Agner's calling convention guide, and, officially, in the recently released version 1.0 of the i386 psABI. Darwin is kept as is because the OS X ABI Function Call Guide explicitly documents the current (4-register) behavior. This fixes PR21510 Differential revision: http://reviews.llvm.org/D9644 llvm-svn: 237682
* Re-land r237175: [X86] Always return the sret parameter in eax/rax ...Reid Kleckner2015-05-181-21/+15
| | | | | | | | | This reverts commit r237210. Also fix X86/complex-fca.ll to match the code that we used to generate on win32 and now generate everwhere to conform to SysV. llvm-svn: 237639
* Simplify IRBuilder::CreateCall* by using ArrayRef+initializer_list/braced ↵David Blaikie2015-05-182-9/+9
| | | | | | init only llvm-svn: 237624
* MachineInstr: Change return value of getOpcode() to unsigned.Matthias Braun2015-05-182-5/+5
| | | | | | | | | This was previously returning int. However there are no negative opcode numbers and more importantly this was needlessly different from MCInstrDesc::getOpcode() (which even is the value returned here) and SDValue::getOpcode()/SDNode::getOpcode(). llvm-svn: 237611
* MC: Clean up method names in MCContext.Jim Grosbach2015-05-187-23/+23
| | | | | | | The naming was a mish-mash of old and new style. Update to be consistent with the new. NFC. llvm-svn: 237594
* AVX-512: Added intrinsics for ADDSS/D, MULSS/D, SUBSS/D, DIVSS/DElena Demikhovsky2015-05-182-2/+27
| | | | | | | | | instructions. These intrinsics are comming with rounding mode. Added intrinsics for MAXSS/D, MINSS/D - with and without sae. By Asaf Badouh (asaf.badouh@intel.com) llvm-svn: 237560
* fixed compilation warning/errorElena Demikhovsky2015-05-181-0/+1
| | | | llvm-svn: 237559
* AVX-512: Added patterns for scalar-to-vector broadcastElena Demikhovsky2015-05-181-0/+10
| | | | llvm-svn: 237558
* AVX-512: Added VBROADCASTF64X4, VBROADCASTF64X2, VBROADCASTI32X8, and other ↵Elena Demikhovsky2015-05-183-12/+61
| | | | | | | | instructions from this set Added encoding tests. llvm-svn: 237557
* AVX-512: fixed extended load to 512-bit registerElena Demikhovsky2015-05-171-2/+2
| | | | llvm-svn: 237537
* AVX-512: fixed a bug in mask operations - (i1 1) patternElena Demikhovsky2015-05-171-2/+2
| | | | | | | Filling k-reg with all-ones value was wrong, (i1 1) should switch on only one bit in mask register llvm-svn: 237536
* [x86] Distinguish the 'o', 'v', 'X', and 'i' inline assembly memory constraints.Daniel Sanders2015-05-162-3/+16
| | | | | | | | | | | | | | | | | | | | | | Summary: But still handle them the same way since I don't know how they differ on this target. Of these, 'o' and 'v' are not tested but were already implemented. I'm not sure why 'i' is required for X86 since it's supposed to be an immediate constraint rather than a memory constraint. A test asserts without it so I've included it for now. No functional change intended. Reviewers: nadav Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8254 llvm-svn: 237517
* MC: Use MCSymbol in RelAndSymbol, NFCDuncan P. N. Exon Smith2015-05-161-10/+6
| | | | | | Switch from `MCSymbolData` to `MCSymbol`. llvm-svn: 237502
* MC: Change MCFragment::Atom to an MCSymbol, NFCDuncan P. N. Exon Smith2015-05-161-12/+16
| | | | | | | Change `MCFragment::Atom` from an `MCSymbolData` to an `MCSymbol`, moving in the direction of removing the back-pointer. llvm-svn: 237497
* Remove MCAssembler.h include from MCStreamer.h and fix users of MCStreamer.hPete Cooper2015-05-151-0/+1
| | | | llvm-svn: 237483
* Remove 3 includes from MCInstrDesc.h and explicitly include them where neededPete Cooper2015-05-153-0/+7
| | | | llvm-svn: 237481
* [X86] Use a better sentinel offset for the FrameAddr indexDavid Majnemer2015-05-151-1/+1
| | | | | | | | | Other pieces of CodeGen want to negate frame object offsets to account for architectures where the stack grows down. Our object is a pseudo object so it's offset doesn't matter. However, we shouldn't choose an offset which results in undefined behavior if you negate it. llvm-svn: 237474
* MC: MCCodeGenInfo naming update. NFC.Jim Grosbach2015-05-151-1/+1
| | | | | | s/InitMCCodeGenInfo/initMCCodeGenInfo/ llvm-svn: 237471
* MC: Update MCCodeEmitter naming. NFC.Jim Grosbach2015-05-152-3/+3
| | | | | | s/EncodeInstruction/encodeInstruction/ llvm-svn: 237469
* MC: Update MCFixup naming. NFC.Jim Grosbach2015-05-151-1/+1
| | | | | | s/MCFixup::Create/MCFixup::create/ llvm-svn: 237468
* Remove setting FloatABIType from the X86 port, nothing uses it.Eric Christopher2015-05-141-4/+0
| | | | llvm-svn: 237398
* AVX-512: Added i1 type handling for calling conventions.Elena Demikhovsky2015-05-142-21/+31
| | | | | | | | i1 type is a legal type on AVX-512 and can be passed as parameter or return value. i1 is promoted to i8 on return and to i32 for call arguments (i8 is also promoted to i32 here). The result code is similar to the previous X86 targets, where i1 is allways promoted to i8. llvm-svn: 237350
* [X86] Fix PR23271 - RIP-relative decoding bug in disassembler.Douglas Katzman2015-05-131-9/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D9110 llvm-svn: 237310
* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-137-83/+82
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
* Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-05-135-31/+31
| | | | | | | The buildbots are still not satisfied. MIPS and ARM are failing (even though at least MIPS was expected to pass). llvm-svn: 237245
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-05-135-31/+31
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
* AVX-512: fixed a bug in encoding of VPSRAQ instrcution,Elena Demikhovsky2015-05-131-1/+1
| | | | | | added a bunch of encoding tests. llvm-svn: 237232
* [Statepoints] Support for "patchable" statepoints.Sanjoy Das2015-05-121-36/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change adds two new parameters to the statepoint intrinsic, `i64 id` and `i32 num_patch_bytes`. `id` gets propagated to the ID field in the generated StackMap section. If the `num_patch_bytes` is non-zero then the statepoint is lowered to `num_patch_bytes` bytes of nops instead of a call (the spill and reload code remains unchanged). A non-zero `num_patch_bytes` is useful in situations where a language runtime requires complete control over how a call is lowered. This change brings statepoints one step closer to patchpoints. With some additional work (that is not part of this patch) it should be possible to get rid of `TargetOpcode::STATEPOINT` altogether. PlaceSafepoints generates `statepoint` wrappers with `id` set to `0xABCDEF00` (the old default value for the ID reported in the stackmap) and `num_patch_bytes` set to `0`. This can be made more sophisticated later. Reviewers: reames, pgavlin, swaroop.sridhar, AndyAyers Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9546 llvm-svn: 237214
* Revert r237175: [X86] Always return the sret parameter in eax/rax ...Chandler Carruth2015-05-121-15/+21
| | | | | | | This commit broke an x86 test and the bots have been broken for well over an hour now so I'm just reverting. llvm-svn: 237210
* [X86] Always return the sret parameter in eax/rax, even on 32-bitReid Kleckner2015-05-121-21/+15
| | | | | | | | | | | | | | | | | | | Summary: This rule was always in the old SysV i386 ABI docs and the new ones that H.J. Lu has put together, but we never noticed: EAX scratch register; also used to return integer and pointer values from functions; also stores the address of a returned struct or union Fixes PR23491. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9715 llvm-svn: 237175
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