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* [WinEH] Put finally pointers in the handler scope table fieldReid Kleckner2015-06-111-1/+1
| | | | | | | | | | We were putting them in the filter field, which is correct for 64-bit but wrong for 32-bit. Also switch the order of scope table entry emission so outermost entries are emitted first, and fix an obvious state assignment bug. llvm-svn: 239574
* [Stackmaps][X86] Remove EFLAGS and IP registers from the live-out mask.Juergen Ributzka2015-06-112-0/+18
| | | | | | | | | | | | | Remove the EFLAGS from the stackmap live-out mask. The EFLAGS register is not supposed to be part of that set, because the X86 calling conventions mark the register as NOT preserved. Also remove the IP registers, since spilling and restoring those doesn't really make any sense. Related to rdar://problem/21019635. llvm-svn: 239568
* [WinEH] Create an llvm.x86.seh.exceptioninfo intrinsicReid Kleckner2015-06-112-47/+42
| | | | | | | | | | | | | | This intrinsic is like framerecover plus a load. It recovers the EH registration stack allocation from the parent frame and loads the exception information field out of it, giving back a pointer to an EXCEPTION_POINTERS struct. It's designed for clang to use in SEH filter expressions instead of accessing the EXCEPTION_POINTERS parameter that is available on x64. This required a minor change to MC to allow defining a label variable to another absolute framerecover label variable. llvm-svn: 239567
* Replace string GNU Triples with llvm::Triple in TargetMachine. NFC.Daniel Sanders2015-06-112-7/+8
| | | | | | | | | | | | | | | | | | Summary: For the moment, TargetMachine::getTargetTriple() still returns a StringRef. This continues the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. Reviewers: rengolin Reviewed By: rengolin Subscribers: ted, llvm-commits, rengolin, jholewinski Differential Revision: http://reviews.llvm.org/D10362 llvm-svn: 239554
* [CodeGen] ArrayRef'ize cond/pred in various TII APIs. NFC.Ahmed Bougacha2015-06-112-11/+6
| | | | llvm-svn: 239553
* [X86][SSE] Vectorized i8 and i16 shift operatorsSimon Pilgrim2015-06-112-38/+174
| | | | | | | | | | | | | | | | This patch ensures that SHL/SRL/SRA shifts for i8 and i16 vectors avoid scalarization. It builds on the existing i8 SHL vectorized implementation of moving the shift bits up to the sign bit position and separating the 4, 2 & 1 bit shifts with several improvements: 1 - SSE41 targets can use (v)pblendvb directly with the sign bit instead of performing a comparison to feed into a VSELECT node. 2 - pre-SSE41 targets were masking + comparing with an 0x80 constant - we avoid this by using the fact that a set sign bit means a negative integer which can be compared against zero to then feed into VSELECT, avoiding the need for a constant mask (zero generation is much cheaper). 3 - SRA i8 needs to be unpacked to the upper byte of a i16 so that the i16 psraw instruction can be correctly used for sign extension - we have to do more work than for SHL/SRL but perf tests indicate that this is still beneficial. The i16 implementation is similar but simpler than for i8 - we have to do 8, 4, 2 & 1 bit shifts but less shift masking is involved. SSE41 use of (v)pblendvb requires that the i16 shift amount is splatted to both bytes however. Tested on SSE2, SSE41 and AVX machines. Differential Revision: http://reviews.llvm.org/D9474 llvm-svn: 239509
* Revert "Move dllimport name mangling to IR mangler."Reid Kleckner2015-06-112-0/+9
| | | | | | | | | This reverts commit r239437. This broke clang-cl self-hosts. We'd end up calling the __imp_ symbol directly instead of using it to do an indirect function call. llvm-svn: 239502
* change assert that will never fire to llvm_unreachableSanjay Patel2015-06-101-1/+1
| | | | llvm-svn: 239497
* [x86] Add a reassociation optimization to increase ILP via the ↵Sanjay Patel2015-06-103-0/+243
| | | | | | | | | | | | | | | | | | MachineCombiner pass This is a reimplementation of D9780 at the machine instruction level rather than the DAG. Use the MachineCombiner pass to reassociate scalar single-precision AVX additions (just a starting point; see the TODO comments) to increase ILP when it's safe to do so. The code is closely based on the existing MachineCombiner optimization that is implemented for AArch64. This patch should not cause the kind of spilling tragedy that led to the reversion of r236031. Differential Revision: http://reviews.llvm.org/D10321 llvm-svn: 239486
* Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and ↵Daniel Sanders2015-06-105-19/+17
| | | | | | | | | | | | | | | | | | create*MCSubtargetInfo(). NFC. Summary: This continues the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. Reviewers: rafael Reviewed By: rafael Subscribers: rafael, ted, jfb, llvm-commits, rengolin, jholewinski Differential Revision: http://reviews.llvm.org/D10311 llvm-svn: 239467
* Replace string GNU Triples with llvm::Triple in create*MCRelocationInfo(). NFC.Daniel Sanders2015-06-101-3/+2
| | | | | | | | | | | | | | | | Summary: This continues the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. Reviewers: rafael Reviewed By: rafael Subscribers: rafael, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10307 llvm-svn: 239465
* Replace string GNU Triples with llvm::Triple in MCAsmBackend subclasses and ↵Daniel Sanders2015-06-102-8/+4
| | | | | | | | | | | | | | | | | | create*AsmBackend(). NFC. Summary: This continues the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. Reviewers: echristo, rafael Reviewed By: rafael Subscribers: rafael, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10243 llvm-svn: 239464
* AVX-512: Fixed a bug in comparison of i1 vectors.Elena Demikhovsky2015-06-102-7/+7
| | | | | | | | | cmp eq should give kxnor instruction cmp neq should give kxor https://llvm.org/bugs/show_bug.cgi?id=23631 llvm-svn: 239460
* [WinEH] Call llvm.stackrestore in __except blocksReid Kleckner2015-06-101-1/+19
| | | | | | | We have to do this manually, the runtime only sets up ebp. Fixes a crash when returning after catching an exception. llvm-svn: 239451
* [WinEH] Emit .safeseh directives for all 32-bit exception handlersReid Kleckner2015-06-101-4/+7
| | | | | | | | | | Use a "safeseh" string attribute to do this. You would think we chould just accumulate the set of personalities like we do on dwarf, but this fails to account for the LSDA-loading thunks we use for __CxxFrameHandler3. Each of those needs to make it into .sxdata as well. The string attribute seemed like the most straightforward approach. llvm-svn: 239448
* Move dllimport name mangling to IR mangler.Peter Collingbourne2015-06-092-9/+0
| | | | | | | | This ensures that LTO clients see the correct external symbol name. Differential Revision: http://reviews.llvm.org/D10318 llvm-svn: 239437
* [WinEH] Add 32-bit SEH state table emission prototypeReid Kleckner2015-06-092-2/+94
| | | | | | | | | | | | This gets all the handler info through to the asm printer and we can look at the .xdata tables now. I've convinced one small catch-all test case to work, but other than that, it would be a stretch to say this is functional. The state numbering algorithm avoids doing any scope reconstruction as we do for C++ to simplify the implementation. llvm-svn: 239433
* Remove DisableTailCalls from TargetOptions and the code in resetTargetOptionsAkira Hatanaka2015-06-091-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | that was resetting it. Remove the uses of DisableTailCalls in subclasses of TargetLowering and use the value of function attribute "disable-tail-calls" instead. Also, unconditionally add pass TailCallElim to the pipeline and check the function attribute at the start of runOnFunction to disable the pass on a per-function basis. This is part of the work to remove TargetMachine::resetTargetOptions, and since DisableTailCalls was the last non-fast-math option that was being reset in that function, we should be able to remove the function entirely after the work to propagate IR-level fast-math flags to DAG nodes is completed. Out-of-tree users should remove the uses of DisableTailCalls and make changes to attach attribute "disable-tail-calls"="true" or "false" to the functions in the IR. rdar://problem/13752163 Differential Revision: http://reviews.llvm.org/D10099 llvm-svn: 239427
* X86-MPX: Implemented encoding for MPX instructions.Elena Demikhovsky2015-06-095-3/+80
| | | | | | Added encoding tests. llvm-svn: 239403
* MC: Add target hook to control symbol quotingMatt Arsenault2015-06-093-15/+24
| | | | llvm-svn: 239370
* [WinEH] Cache declarations of frame intrinsicsReid Kleckner2015-06-081-6/+10
| | | | llvm-svn: 239361
* [InstrInfo] Refactor foldOperandImpl to thread through InsertPt. NFCKeno Fischer2015-06-083-45/+50
| | | | | | | | | | | | | | | | | | Summary: This was a longstanding FIXME and is a necessary precursor to cases where foldOperandImpl may have to create more than one instruction (e.g. to constrain a register class). This is the split out NFC changes from D6262. Reviewers: pete, ributzka, uweigand, mcrosier Reviewed By: mcrosier Subscribers: mcrosier, ted, llvm-commits Differential Revision: http://reviews.llvm.org/D10174 llvm-svn: 239336
* X86: Reject register operands with obvious type mismatches.Matthias Braun2015-06-081-0/+13
| | | | | | | | | | | | | While we have some code to transform specification like {ax} into {eax}/{rax} if the operand type isn't 16bit, we should reject cases where there is no sane way to do this, like the i128 type in the example. Related to rdar://21042280 Differential Revision: http://reviews.llvm.org/D10260 llvm-svn: 239309
* AVX-512: Implemented 256/128bit VALIGND/Q instructions for SKX and KNLIgor Breger2015-06-084-39/+59
| | | | | | | | | Implemented DAG lowering for all these forms. Added tests for DAG lowering and encoding. Differential Revision: http://reviews.llvm.org/D10310 llvm-svn: 239300
* [X86] Added BitScanForward/BitScanReverse memory folding + testsSimon Pilgrim2015-06-071-0/+6
| | | | llvm-svn: 239257
* Handle 16 bit PC relative relocations.Rafael Espindola2015-06-061-0/+1
| | | | | | Fixes pr23771. llvm-svn: 239214
* MC: Clean up the naming for MCMachObjectWriter. NFC.Jim Grosbach2015-06-041-8/+8
| | | | | | | | | | | | | | | | | | s/ExecutePostLayoutBinding/executePostLayoutBinding/ s/ComputeSymbolTable/computeSymbolTable/ s/BindIndirectSymbols/bindIndirectSymbols/ s/RecordTLVPRelocation/recordTLVPRelocation/ s/RecordScatteredRelocation/recordScatteredRelocation/ s/WriteLinkerOptionsLoadCommand/writeLinkerOptionsLoadCommand/ s/WriteLinkeditLoadCommand/writeLinkeditLoadCommand/ s/WriteNlist/writeNlist/ s/WriteDysymtabLoadCommand/writeDysymtabLoadCommand/ s/WriteSymtabLoadCommand/writeSymtabLoadCommand/ s/WriteSection/writeSection/ s/WriteSegmentLoadCommand/writeSegmentLoadCommand/ s/WriteHeader/writeHeader/ llvm-svn: 239119
* [Target/X86] Don't use callee-saved registers in a Win64 tail call on ↵Charles Davis2015-06-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | non-Windows. Summary: A small bit that I missed when I updated the X86 backend to account for the Win64 calling convention on non-Windows. Now we don't use dead non-volatile registers when emitting a Win64 indirect tail call on non-Windows. Should fix PR23710. Test Plan: Added test for the correct behavior based on the case I posted to PR23710. Reviewers: rnk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10258 llvm-svn: 239111
* MC: Clean up naming in MCObjectWriter. NFC.Jim Grosbach2015-06-042-4/+4
| | | | | | | | | | | | | | | | | | | | s/WriteObject/writeObject/ s/RecordRelocation/recordRelocation/ s/IsSymbolRefDifferenceFullyResolved/isSymbolRefDifferenceFullyResolved/ s/Write8/write8/ s/WriteLE16/writeLE16/ s/WriteLE32/writeLE32/ s/WriteLE64/writeLE64/ s/WriteBE16/writeBE16/ s/WriteBE32/writeBE32/ s/WriteBE64/writeBE64/ s/Write16/write16/ s/Write32/write32/ s/Write64/write64/ s/WriteZeroes/writeZeroes/ s/WriteBytes/writeBytes/ llvm-svn: 239108
* MC: Remove obsolete MachO UseAggressiveSymbolFolding.Jim Grosbach2015-06-041-4/+2
| | | | | | | | | | Fix the FIXME and remove this old as(1) compat option. It was useful for bringup of the integrated assembler to diff object files, but now it's just causing more relocations than strictly necessary to be generated. rdar://21201804 llvm-svn: 239084
* Replace string GNU Triples with llvm::Triple in MCAsmInfo subclasses and ↵Daniel Sanders2015-06-041-2/+2
| | | | | | | | | | | | | | | | | | | | create*AsmInfo(). NFC. Summary: This is the first of several patches to eliminate StringRef forms of GNU triples from the internals of LLVM. After this is complete, GNU triples will be replaced by a more authoratitive representation in the form of an LLVM TargetTuple. Reviewers: rengolin Reviewed By: rengolin Subscribers: ted, llvm-commits, rengolin, jholewinski Differential Revision: http://reviews.llvm.org/D10236 llvm-svn: 239036
* AVX-512: I brought back vector-shuffle-512-v8.ll test.Elena Demikhovsky2015-06-041-1/+2
| | | | | | I re-generated it after all AVX-512 shuffle optimizations. llvm-svn: 239026
* AVX-512: added all SKX forms of VPERMW/D/Q instructions.Elena Demikhovsky2015-06-041-38/+50
| | | | | | | Added all forms of VPERMPS/PD instrcuctions. Added encoding tests. llvm-svn: 239016
* Removed {}, NFC.Elena Demikhovsky2015-06-041-2/+1
| | | | llvm-svn: 239014
* make reciprocal estimate code generation more flexible by adding ↵Sanjay Patel2015-06-045-54/+41
| | | | | | | | | | | | | | | | | | | | | | command-line options (3rd try) The first try (r238051) to land this was reverted due to ExecutionEngine build failure; that was hopefully addressed by r238788. The second try (r238842) to land this was reverted due to BUILD_SHARED_LIBS failure; that was hopefully addressed by r238953. This patch adds a TargetRecip class for processing many recip codegen possibilities. The class is intended to handle both command-line options to llc as well as options passed in from a front-end such as clang with the -mrecip option. The x86 backend is updated to use the new functionality. Only -mcpu=btver2 with -ffast-math should see a functional change from this patch. All other x86 CPUs continue to *not* use reciprocal estimates by default with -ffast-math. Differential Revision: http://reviews.llvm.org/D8982 llvm-svn: 239001
* re-apply 238809Asaf Badouh2015-06-035-25/+107
| | | | | | | | | | AVX-512: Implemented GETEXP instruction for KNL and SKX Added rounding mode modifier for SQRTPS/PD Added tests for encoding and intrinsics. CR: http://reviews.llvm.org/D9991 llvm-svn: 238923
* AVX-512: More code improvements in shuffles, NFCElena Demikhovsky2015-06-031-21/+19
| | | | llvm-svn: 238919
* AVX-512: VSHUFPD instruction selection - code improvementsElena Demikhovsky2015-06-031-34/+36
| | | | llvm-svn: 238918
* AVX-512: Implemented SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2 instructions ↵Elena Demikhovsky2015-06-034-9/+61
| | | | | | | | | | for SKX and KNL. Added tests for encoding. By Igor Breger (igor.breger@intel.com) llvm-svn: 238917
* X86: Added MPX feature and bound registers.Elena Demikhovsky2015-06-035-2/+18
| | | | | | | | | Intel® Memory Protection Extensions (Intel® MPX) is a new feature in Skylake. It is a part of KNL and SKX sets. It is also a part of Skylake client. I added definition of %bnd0 - %bnd3 registers, each register is a pair of 64-bit integers. llvm-svn: 238916
* [X86] Removed (unused) FSRL x86 operationSimon Pilgrim2015-06-034-21/+3
| | | | | | | | | | This patch removes the old X86ISD::FSRL op - which allowed float vectors to use the byte right shift operations (causing a domain switch....). Since the refactoring of the shuffle lowering code this no longer has any use. Differential Revision: http://reviews.llvm.org/D10169 llvm-svn: 238906
* Revert "make reciprocal estimate code generation more flexible by adding ↵Rafael Espindola2015-06-035-41/+54
| | | | | | | | | | command-line options (2nd try)" This reverts commit r238842. It broke -DBUILD_SHARED_LIBS=ON build. llvm-svn: 238900
* Avoid a call to getOrCreateSymbol when we already have the symbol.Rafael Espindola2015-06-031-2/+5
| | | | llvm-svn: 238890
* make reciprocal estimate code generation more flexible by adding ↵Sanjay Patel2015-06-025-54/+41
| | | | | | | | | | | | | | | | | | | command-line options (2nd try) The first try (r238051) to land this was reverted due to bot failures that were hopefully addressed by r238788. This patch adds a TargetRecip class for processing many recip codegen possibilities. The class is intended to handle both command-line options to llc as well as options passed in from a front-end such as clang with the -mrecip option. The x86 backend is updated to use the new functionality. Only -mcpu=btver2 with -ffast-math should see a functional change from this patch. All other x86 CPUs continue to *not* use reciprocal estimates by default with -ffast-math. Differential Revision: http://reviews.llvm.org/D8982 llvm-svn: 238842
* AVX-512: Implemented VRANGESD and VRANGESS instructions for SKX Implemented ↵Elena Demikhovsky2015-06-021-0/+7
| | | | | | | | | | DAG lowering for all these forms. Added tests for encoding. By Igor Breger (igor.breger@intel.com) llvm-svn: 238834
* AVX-512: Shorten implementation of lowerV16X32VectorShuffle()Elena Demikhovsky2015-06-021-39/+61
| | | | | | | using lowerVectorShuffleWithSHUFPS() and other shuffle-helpers routines. Added matching of VALIGN instruction. llvm-svn: 238830
* AVX-512: Implemented VFIXUPIMMSD and VFIXUPIMMSS instructions for KNLElena Demikhovsky2015-06-021-14/+51
| | | | | | | | | Implemented DAG lowering for all these forms. Added tests for encoding. By Igor Breger (igor.breger@intel.com) llvm-svn: 238811
* revert 238809Asaf Badouh2015-06-025-107/+25
| | | | llvm-svn: 238810
* AVX-512: Implemented GETEXP instruction for KNL and SKXAsaf Badouh2015-06-025-25/+107
| | | | | | | Added rounding mode modifier for SQRTPS/PD Added tests for encoding and intrinsics. llvm-svn: 238809
* AVX-512: Optimized vector shuffle for v16f32 and v16i32 types.Elena Demikhovsky2015-06-011-36/+48
| | | | llvm-svn: 238743
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