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* [X86] Don't try to generate direct calls to TLS globalsMichael Kuperstein2015-01-081-1/+2
| | | | | | | | | The call lowering assumes that if the callee is a global, we want to emit a direct call. This is correct for regular globals, but not for TLS ones. Differential Revision: http://reviews.llvm.org/D6862 llvm-svn: 225438
* [X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the ↵Craig Topper2015-01-084-4/+14
| | | | | | LEA variants in Intel syntax. The memory operand is inherently unsized. llvm-svn: 225432
* [SelectionDAG] Allow targets to specify legality of extloads' resultAhmed Bougacha2015-01-081-26/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | type (in addition to the memory type). The *LoadExt* legalization handling used to only have one type, the memory type. This forced users to assume that as long as the extload for the memory type was declared legal, and the result type was legal, the whole extload was legal. However, this isn't always the case. For instance, on X86, with AVX, this is legal: v4i32 load, zext from v4i8 but this isn't: v4i64 load, zext from v4i8 Whereas v4i64 is (arguably) legal, even without AVX2. Note that the same thing was done a while ago for truncstores (r46140), but I assume no one needed it yet for extloads, so here we go. Calls to getLoadExtAction were changed to add the value type, found manually in the surrounding code. Calls to setLoadExtAction were mechanically changed, by wrapping the call in a loop, to match previous behavior. The loop iterates over the MVT subrange corresponding to the memory type (FP vectors, etc...). I also pulled neighboring setTruncStoreActions into some of the loops; those shouldn't make a difference, as the additional types are illegal. (e.g., i128->i1 truncstores on PPC.) No functional change intended. Differential Revision: http://reviews.llvm.org/D6532 llvm-svn: 225421
* X86: VZeroUpperInserter: shortcut should not trigger if we have any function ↵Matthias Braun2015-01-081-8/+12
| | | | | | live-ins. llvm-svn: 225419
* [CodeGen] Use MVT iterator_ranges in legality loops. NFC intended.Ahmed Bougacha2015-01-071-26/+9
| | | | | | | | A few loops do trickier things than just iterating on an MVT subset, so I'll leave them be for now. Follow-up of r225387. llvm-svn: 225392
* [X86] Fix 512->256 typo in comments. NFC.Ahmed Bougacha2015-01-071-2/+2
| | | | llvm-svn: 225367
* X86: Allow the stack probe size to be configurable per functionDavid Majnemer2015-01-071-3/+9
| | | | | | | | | | | | | | | | | | | LLVM emits stack probes on Windows targets to ensure that the stack is correctly accessed. However, the amount of stack allocated before emitting such a probe is hardcoded to 4096. It is desirable to have this be configurable so that a function might opt-out of stack probes. Our level of granularity is at the function level instead of, say, the module level to permit proper generation of code after LTO. Patch by Andrew H! N.B. The inliner needs to be updated to properly consider what happens after inlining a function with a specific stack-probe-size into another function with a different stack-probe-size. llvm-svn: 225360
* [X86] Teach FCOPYSIGN lowering to recognize constant magnitudes.Ahmed Bougacha2015-01-071-6/+19
| | | | | | | | | | | | | | | | | | | | | For code like: float foo(float x) { return copysign(1.0, x); } We used to generate: andps <-0.000000e+00,0,0,0>, %xmm0 movss <1.000000e+00>, %xmm1 andps <nan>, %xmm1 orps %xmm0, %xmm1 Basically doing an abs(1.0f) in the two middle instructions. We now generate: andps <-0.000000e+00,0,0,0>, %xmm0 orps <1.000000e+00,0,0,0>, %xmm0 Builds on cleanups r223415, r223542. rdar://19049548 Differential Revision: http://reviews.llvm.org/D6555 llvm-svn: 225357
* [X86] Merge a switch statement inside a default case of another switch ↵Craig Topper2015-01-071-160/+155
| | | | | | statement on the same variable. There was no additional code in the default so this should be no functional change. llvm-svn: 225345
* [X86] Don't mark the shift by 1 instructions as isConvertibleToThreeAddress. ↵Craig Topper2015-01-071-1/+1
| | | | | | There is no handling for them. llvm-svn: 225344
* [X86] Remove some unused TYPE enums from the disassembler.Craig Topper2015-01-073-18/+1
| | | | llvm-svn: 225343
* Revert r224935 "Refactor duplicated code. No intended functionality change."Lang Hames2015-01-062-2/+21
| | | | | | | | This is affecting the behavior of some ObjC++ / AArch64 test cases on Darwin. Reverting to get the bots green while I track down the source of the changed behavior. llvm-svn: 225311
* [X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16.Craig Topper2015-01-064-7/+40
| | | | | | Requires new AsmParserOperand types that detect 16-bit and 32/64-bit mode so that we choose the right instruction based on default sizing without predicates. This is necessary since predicates mess up the disassembler table building. llvm-svn: 225256
* [X86] Make isel select the 2-byte register form of INC/DEC even in ↵Craig Topper2015-01-065-126/+78
| | | | | | | | non-64-bit mode. Convert to the 1-byte form in non-64-bit mode as part of MCInst lowering. Overall this seems simpler. It reduces duplication of patterns between both modes and it simplifies the memory folding/unfolding tables as they don't need to create fake instructions just to keep track of 64-bitness. llvm-svn: 225252
* X86: Don't make illegal GOTTPOFF relocationsDavid Majnemer2015-01-062-0/+17
| | | | | | | | | | | | | "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF relocation target a movq or addq instruction. Prohibit the truncation of such loads to movl or addl. This fixes PR22083. Differential Revision: http://reviews.llvm.org/D6839 llvm-svn: 225250
* [X86] Remove 16-bit and 32-bit offset jump instructions from the AsmParser. ↵Craig Topper2015-01-061-2/+2
| | | | | | We always select the 8-bit size and let the assembler backend relax to the larger size. llvm-svn: 225243
* [X86] Make isel select the shorter form of jump instructions instead of the ↵Craig Topper2015-01-068-120/+97
| | | | | | | | long form. The assembler backend will relax to the long form if necessary. This removes a swap from long form to short form in the MCInstLowering code. Selecting the long form used to be required by the old JIT. llvm-svn: 225242
* Revert r225048: It broke ObjC on AArch64.Lang Hames2015-01-062-46/+83
| | | | | | I've filed http://llvm.org/PR22100 to track this issue. llvm-svn: 225228
* Remove X86 .quad workaround for buggy GNU assembler on OpenBSD / Bitrig.Brad Smith2015-01-061-5/+0
| | | | llvm-svn: 225227
* [X86][SSE] lowerVectorShuffleAsByteShift tidyupSimon Pilgrim2015-01-051-21/+14
| | | | | | Removed local isSequential predicate and use standard helper isSequentialOrUndefInRange instead. llvm-svn: 225216
* [X86][SSE] Fixed description for isSequentialOrUndefInRange. NFC.Simon Pilgrim2015-01-051-1/+1
| | | | llvm-svn: 225202
* Replace several 'assert(false' with 'llvm_unreachable' or fold a condition ↵Craig Topper2015-01-052-14/+5
| | | | | | into the assert. llvm-svn: 225160
* [X86] Remove the predicates from the register forms of the 2-byte inc and ↵Craig Topper2015-01-052-44/+24
| | | | | | dec instructions. Remove the 32-bit mode only versions that existed for the disassembler. Move the patterns out of the instructions so they can still be qualified with predicates. llvm-svn: 225157
* [X86] Simplify code a little by just summing flags instead of conditionally ↵Craig Topper2015-01-051-18/+7
| | | | | | incrementing. NFC llvm-svn: 225156
* [X86] Remove unnecessary redeclaration of a variable with the same ↵Craig Topper2015-01-051-1/+0
| | | | | | assignment as the beginning of the function. NFC. llvm-svn: 225155
* [X86] Remove a strange fixme referring to a hack that doesn't seem to exist ↵Craig Topper2015-01-051-3/+0
| | | | | | since the code is in a comment. Can't figure out what the body of the 'if' was supposed to be anyway. llvm-svn: 225154
* [x86] Reduce text duplication for similar operand class declarations in ↵Craig Topper2015-01-051-268/+178
| | | | | | tablegen instruction info. No functional change intended. llvm-svn: 225153
* [X86] Fix the immediate size to match the address size in the operand types ↵Craig Topper2015-01-051-7/+7
| | | | | | for the move to/from absolute memory instructions. llvm-svn: 225152
* Minor cleanup to all the switches after MatchInstructionImpl in all the ↵Craig Topper2015-01-031-1/+1
| | | | | | | | AsmParsers. Make sure they all have llvm_unreachable on the default path out of the switch. Remove unnecessary "default: break". Remove a 'return' after unreachable. Fix some indentation. llvm-svn: 225114
* [X86] Disassembler support for move to/from %rax with a 32-bit memory offset ↵Craig Topper2015-01-033-0/+22
| | | | | | is REX.W and AdSize prefix are both present. llvm-svn: 225099
* [X86] Use 32-bit sign extended immediate for 64-bit LOCK_ArithBinOp with ↵Craig Topper2015-01-031-6/+6
| | | | | | sign extended immediate. llvm-svn: 225098
* Improved comments. No functional change intended.Andrea Di Biagio2015-01-021-2/+2
| | | | llvm-svn: 225080
* [X86] Bring some better consistency to the naming of the move to/from ↵Craig Topper2015-01-022-44/+41
| | | | | | %al/ax/eax/rax with memory offset. llvm-svn: 225078
* [X86] Make the instructions that use AdSize16/32/64 co-exist together ↵Craig Topper2015-01-025-144/+241
| | | | | | | | | | without using mode predicates. This is necessary to allow the disassembler to be able to handle AdSize32 instructions in 64-bit mode when address size prefix is used. Eventually we should probably also support 'addr32' and 'addr16' in the assembler to override the address size on some of these instructions. But for now we'll just use special operand types that will lookup the current mode size to select the right instruction. llvm-svn: 225075
* Add r224985 back with a fix.Rafael Espindola2014-12-312-83/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The issues was that AArch64 has additional restrictions on when local relocations can be used. We have to take those into consideration when deciding to put a L symbol in the symbol table or not. Original message: Remove doesSectionRequireSymbols. In an assembly expression like bar: .long L0 + 1 the intended semantics is that bar will contain a pointer one byte past L0. In sections that are merged by content (strings, 4 byte constants, etc), a single position in the section doesn't give the linker enough information. For example, it would not be able to tell a relocation must point to the end of a string, since that would look just like the start of the next. The solution used in ELF to use relocation with symbols if there is a non-zero addend. In MachO before this patch we would just keep all symbols in some sections. This would miss some cases (only cstrings on x86_64 were implemented) and was inefficient since most relocations have an addend of 0 and can be represented without the symbol. This patch implements the non-zero addend logic for MachO too. llvm-svn: 225048
* Revert "Remove doesSectionRequireSymbols."Rafael Espindola2014-12-312-46/+83
| | | | | | | | This reverts commit r224985. I am investigating why it made an Apple bot unhappy. llvm-svn: 225044
* [X86] Fix disassembly of absolute moves to work correctly in 16 and 32-bit ↵Craig Topper2014-12-312-6/+35
| | | | | | modes with all 4 combinations of OpSize and AdSize prefixes being present or not. llvm-svn: 225036
* [x86] Simplify detection of jcxz/jecxz/jrcxz in disassembler.Craig Topper2014-12-311-16/+5
| | | | llvm-svn: 225035
* x86_64: Fix calls to __morestack under the large code model.Peter Collingbourne2014-12-301-6/+30
| | | | | | | | | | | | | | | | | | | | Under the large code model, we cannot assume that __morestack lives within 2^31 bytes of the call site, so we cannot use pc-relative addressing. We cannot perform the call via a temporary register, as the rax register may be used to store the static chain, and all other suitable registers may be either callee-save or used for parameter passing. We cannot use the stack at this point either because __morestack manipulates the stack directly. To avoid these issues, perform an indirect call via a read-only memory location containing the address. This solution is not perfect, as it assumes that the .rodata section is laid out within 2^31 bytes of each function body, but this seems to be sufficient for JIT. Differential Revision: http://reviews.llvm.org/D6787 llvm-svn: 225003
* Remove doesSectionRequireSymbols.Rafael Espindola2014-12-302-83/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | In an assembly expression like bar: .long L0 + 1 the intended semantics is that bar will contain a pointer one byte past L0. In sections that are merged by content (strings, 4 byte constants, etc), a single position in the section doesn't give the linker enough information. For example, it would not be able to tell a relocation must point to the end of a string, since that would look just like the start of the next. The solution used in ELF to use relocation with symbols if there is a non-zero addend. In MachO before this patch we would just keep all symbols in some sections. This would miss some cases (only cstrings on x86_64 were implemented) and was inefficient since most relocations have an addend of 0 and can be represented without the symbol. This patch implements the non-zero addend logic for MachO too. llvm-svn: 224985
* [X86] Fix some cases where some 8-bit instructions were marked as being ↵Craig Topper2014-12-291-18/+24
| | | | | | convertible to three address instructions, but aren't really. llvm-svn: 224940
* [X86] Add the 0x82 instructions to the disassebmler. They are identical in ↵Craig Topper2014-12-291-6/+35
| | | | | | functionality to the 0x80 opcode instructions, but are not valid in 64-bit mode. llvm-svn: 224939
* [x86] Refactor some tablegen instruction info classes slightly to prepare ↵Craig Topper2014-12-291-29/+28
| | | | | | for another change. NFC. llvm-svn: 224938
* [x86] Remove unused classes from tablegen instruction info.Craig Topper2014-12-291-23/+0
| | | | llvm-svn: 224937
* Add segmented stack support for DragonFlyBSD.Rafael Espindola2014-12-292-3/+12
| | | | | | Patch by Michael Neumann. llvm-svn: 224936
* Refactor duplicated code.Rafael Espindola2014-12-292-21/+2
| | | | | | No intended functionality change. llvm-svn: 224935
* [X86][ISel] Fix a regression I introduced in r224884Keno Fischer2014-12-281-3/+3
| | | | | | | | | | | | | The else case ResultReg was not checked for validity. To my surprise, this case was not hit in any of the existing test cases. This includes a new test cases that tests this path. Also drop the `target triple` declaration from the original test as suggested by H.J. Lu, because apparently with it the test won't be run on Linux llvm-svn: 224901
* [X86] Add missing memory variants to AVX false dependency breakingMichael Kuperstein2014-12-281-2/+26
| | | | | | | | Adds missing memory instruction variants to AVX false dependency breaking handling. (SSE was handled in r224246) Differential Revision: http://reviews.llvm.org/D6780 llvm-svn: 224900
* [CodeGenPrepare] Teach when it is profitable to speculate calls to ↵Andrea Di Biagio2014-12-282-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | @llvm.cttz/ctlz. If the control flow is modelling an if-statement where the only instruction in the 'then' basic block (excluding the terminator) is a call to cttz/ctlz, CodeGenPrepare can try to speculate the cttz/ctlz call and simplify the control flow graph. Example: \code entry: %cmp = icmp eq i64 %val, 0 br i1 %cmp, label %end.bb, label %then.bb then.bb: %c = tail call i64 @llvm.cttz.i64(i64 %val, i1 true) br label %end.bb end.bb: %cond = phi i64 [ %c, %then.bb ], [ 64, %entry] \code In this example, basic block %then.bb is taken if value %val is not zero. Also, the phi node in %end.bb would propagate the size-of in bits of %val only if %val is equal to zero. With this patch, CodeGenPrepare will try to hoist the call to cttz from %then.bb into basic block %entry only if cttz is cheap to speculate for the target. Added two new hooks in TargetLowering.h to let targets customize the behavior (i.e. decide whether it is cheap or not to speculate calls to cttz/ctlz). The two new methods are 'isCheapToSpeculateCtlz' and 'isCheapToSpeculateCttz'. By default, both methods return 'false'. On X86, method 'isCheapToSpeculateCtlz' returns true only if the target has LZCNT. Method 'isCheapToSpeculateCttz' only returns true if the target has BMI. Differential Revision: http://reviews.llvm.org/D6728 llvm-svn: 224899
* [x86] Prevent instruction selection of AVX512 cmp.ps/pd/ss/sd intrinsics ↵Craig Topper2014-12-272-22/+23
| | | | | | with illegal immediates. Correctly this time. I did the wrong patterns the first time. llvm-svn: 224891
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