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* Fix copy and paste bug from r186491 to make v2f64 use MOVAPD/MOVUPD as it ↵Craig Topper2013-07-181-2/+2
| | | | | | should. llvm-svn: 186566
* Teach x86 fast-isel to use AVX opcodes for vector stores when AVX is enabled.Craig Topper2013-07-171-6/+6
| | | | llvm-svn: 186496
* Make x86 fast-isel correctly choose between aligned and unaligned operations ↵Craig Topper2013-07-171-12/+28
| | | | | | for vector stores. Fixes PR16640. llvm-svn: 186491
* [X86] Use min/max to optimze unsigend vector comparison on X86Juergen Ributzka2013-07-161-2/+22
| | | | | | | | | | | | | Use PMIN/PMAX for UGE/ULE vector comparions to reduce the number of required instructions. This trick also works for UGT/ULT, but there is no advantage in doing so. It wouldn't reduce the number of instructions and it would actually reduce performance. Reviewer: Ben radar:5972691 llvm-svn: 186432
* Add 'static' keyword to some const arrays for consistency.Craig Topper2013-07-151-6/+6
| | | | llvm-svn: 186308
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-141-4/+4
| | | | | | size. llvm-svn: 186274
* X86 cost model: Add cost for vectorized gather/scatherArnold Schwaighofer2013-07-121-0/+15
| | | | | | radar://14351991 llvm-svn: 186189
* X86: Shrink certain forms of movsx.Benjamin Kramer2013-07-121-0/+35
| | | | | | | | | | | | In particular: movsbw %al, %ax --> cbtw movswl %ax, %eax --> cwtl movslq %eax, %rax --> cltq According to Intel's manual those have the same performance characteristics but come with a smaller encoding. llvm-svn: 186174
* X86: fold SSE2/AVX2 logical shift by immediate amount into zero vector when ↵Stephen Lin2013-07-121-0/+38
| | | | | | | | possible Patch by Andrea Di Biagio llvm-svn: 186165
* Target/X86: Add explicit Win64 and System V/x86-64 calling conventions.Charles Davis2013-07-124-25/+45
| | | | | | | | | | | | | | | Summary: This patch adds explicit calling convention types for the Win64 and System V/x86-64 ABIs. This allows code to override the default, and use the Win64 convention on a target that wants to use SysV (and vice-versa). This is needed to implement the `ms_abi` and `sysv_abi` GNU attributes. Reviewers: CC: llvm-svn: 186144
* AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and allStephen Lin2013-07-092-5/+26
| | | | | | | | | | | | | | | | | | | | | | | in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in order to resolve the following issues with fmuladd (i.e. optional FMA) intrinsics: 1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd intrinsics even if the subtarget does not support FMA instructions, leading to laughably bad code generation in some situations. 2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128, resulting in a call to a software fp128 FMA implementation. 3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize, etc. to types that support hardware FMAs. The function has also been slightly renamed for consistency and to force a merge/build conflict for any out-of-tree target implementing it. To resolve, see comments and fixed in-tree examples. llvm-svn: 185956
* X86: Add comment.Jim Grosbach2013-07-091-0/+5
| | | | llvm-svn: 185900
* X86 fast-isel: Avoid explicit AH subreg reference for [SU]Rem.Jim Grosbach2013-07-091-4/+31
| | | | | | | | | | | | | Explicit references to %AH for an i8 remainder instruction can lead to references to %AH in a REX prefixed instruction, which causes things to blow up. Do the same thing in FastISel as we do for DAG isel and instead shift %AX right by 8 bits and then extract the 8-bit subreg from that result. rdar://14203849 http://llvm.org/bugs/show_bug.cgi?id=16105 llvm-svn: 185899
* Reuse %rax after calling __chkstk on win64Nico Rieck2013-07-082-7/+9
| | | | | | Reapply this as I reverted the wrong commit. llvm-svn: 185807
* Revert "Proper va_arg/va_copy lowering on win64"Nico Rieck2013-07-081-3/+1
| | | | | | | | This reverts commit 2b52880592a525cfe04d8f9008a35da8c2ea94c3. Needs review. llvm-svn: 185806
* Revert "Reuse %rax after calling __chkstk on win64"Nico Rieck2013-07-082-9/+7
| | | | | | This reverts commit 01f8d579f7672872324208ac5bc4ac311e81b22e. llvm-svn: 185781
* Reuse %rax after calling __chkstk on win64Nico Rieck2013-07-072-7/+9
| | | | llvm-svn: 185778
* Proper va_arg/va_copy lowering on win64Nico Rieck2013-07-061-1/+3
| | | | llvm-svn: 185763
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-041-4/+0
| | | | | | These exception-related opcodes are not used any longer. llvm-svn: 185625
* Revert r185595-185596 which broke buildbots.Jakob Stoklund Olesen2013-07-041-0/+4
| | | | | | | Revert "Simplify landing pad lowering." Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes." llvm-svn: 185600
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-031-4/+0
| | | | | | These exception-related opcodes are not used any longer. llvm-svn: 185596
* Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid ↵Craig Topper2013-07-031-1/+1
| | | | | | specifying the vector size. llvm-svn: 185540
* [DebugInfo] Allow getDebugThreadLocalSymbol to return MCExprUlrich Weigand2013-07-022-2/+2
| | | | | | | | | | | This allows getDebugThreadLocalSymbol to return a generic MCExpr instead of just a MCSymbolRefExpr. This is in preparation for supporting debug info for TLS variables on PowerPC, where we need to describe the variable location using a more complex expression than just MCSymbolRefExpr. llvm-svn: 185460
* PR16493: DebugInfo with TLS on PPC crashing due to invalid relocationDavid Blaikie2013-07-012-0/+9
| | | | | | | | Restrict the current TLS support to X86 ELF for now. Test that we don't produce it on PPC & we can flesh that test case out with the right thing once someone implements it. llvm-svn: 185389
* X86: POP*rmm: move address operand to (ins) from (outs).Ahmed Bougacha2013-06-301-3/+3
| | | | llvm-svn: 185292
* Fix an off-by-one error. Also make the code a little more explicit in what itChad Rosier2013-06-281-3/+4
| | | | | | is trying to do. llvm-svn: 185191
* Integrate Assembler: Support X86_64_DTPOFF64 relocationsDavid Blaikie2013-06-281-1/+12
| | | | llvm-svn: 185131
* Get rid of the unused class member.Nadav Rotem2013-06-271-3/+2
| | | | llvm-svn: 185086
* CostModel: improve the cost model for load/store of non power-of-two types ↵Nadav Rotem2013-06-271-0/+43
| | | | | | such as <3 x float>, which are popular in graphics. llvm-svn: 185085
* Don't cast away constness.Benjamin Kramer2013-06-271-1/+2
| | | | llvm-svn: 185071
* Optimized integer vector multiplication operation by replacing it with ↵Elena Demikhovsky2013-06-261-2/+4
| | | | | | shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector. llvm-svn: 184931
* X86 cost model: Vectorizing integer division is a bad ideaArnold Schwaighofer2013-06-251-0/+25
| | | | | | radar://14057959 llvm-svn: 184872
* Revert "Temporarily enable MI-Sched on X86."Andrew Trick2013-06-251-4/+1
| | | | | | This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c. llvm-svn: 184823
* Temporarily enable MI-Sched on X86.Andrew Trick2013-06-241-1/+4
| | | | | | | Sorry for the unit test churn. I'll try to make the change permanently next time. llvm-svn: 184705
* Add MI-Sched support for x86 macro fusion.Andrew Trick2013-06-232-0/+164
| | | | | | | | This is an awful implementation of the target hook. But we don't have abstractions yet for common machine ops, and I don't see any quick way to make it table-driven. llvm-svn: 184664
* The getRegForInlineAsmConstraint function should only accept MVT value types.Chad Rosier2013-06-222-3/+3
| | | | llvm-svn: 184642
* DebugInfo: Don't lose unreferenced non-trivial by-value parametersDavid Blaikie2013-06-211-2/+0
| | | | | | | | | | | | A FastISel optimization was causing us to emit no information for such parameters & when they go missing we end up emitting a different function type. By avoiding that shortcut we not only get types correct (very important) but also location information (handy) - even if it's only live at the start of a function & may be clobbered later. Reviewed/discussion by Evan Cheng & Dan Gohman. llvm-svn: 184604
* Fix IMULX machine model. Multiple def operands require multiple SchedWrites.Andrew Trick2013-06-214-4/+7
| | | | llvm-svn: 184566
* Update the X86 disassembler to use xacquire and xrelease when appropriate.Kevin Enderby2013-06-203-0/+32
| | | | | | | | | | | | | | | | | This is a bit tricky as the xacquire and xrelease hints use the same bytes, 0xf2 and 0xf3, as the repne and rep prefixes. Fortunately llvm has different llvm MCInst Opcode enums for rep/xrelease and repne/xacquire. So to make this work a boolean was added the InternalInstruction struct as part of the Prefix state which is set with the added logic in readPrefixes() when decoding an instruction to determine if these prefix bytes are to be disassembled as xacquire or xrelease. Then we let the matcher pick the normal prefix instructionID and we change the Opcode after that when it is set into the MCInst being created. rdar://11019859 llvm-svn: 184490
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-191-9/+7
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184360
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-191-1/+1
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184349
* Fix 80 col violation.Nadav Rotem2013-06-181-3/+6
| | | | llvm-svn: 184228
* Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.Stefanus Du Toit2013-06-181-0/+7
| | | | | | | | For decoding, keep the current behavior of always decoding these as their REP versions. In the future, this could be improved to recognize the cases where these behave as XACQUIRE and XRELEASE and decode them as such. llvm-svn: 184207
* Use pointers to the MCAsmInfo and MCRegInfo.Bill Wendling2013-06-182-3/+3
| | | | | | | | | Someone may want to do something crazy, like replace these objects if they change or something. No functionality change intended. llvm-svn: 184175
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE ↵David Blaikie2013-06-165-73/+1
| | | | | | | | | | MachineInstrs Frame index handling is now target-agnostic, so delete the target hooks for creation & asm printing of target-specific addressing in DBG_VALUEs and any related functions. llvm-svn: 184067
* Support BufferSize on ProcResGroup for unified MOp schedulers.Andrew Trick2013-06-152-0/+11
| | | | | | And add Sandybridge/Haswell resource buffers. llvm-svn: 184034
* Update machine models. Specify buffer sizes for OOO processors.Andrew Trick2013-06-154-7/+7
| | | | llvm-svn: 184033
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-154-8/+0
| | | | | | | | | | | | | Replace the ill-defined MinLatency and ILPWindow properties with with straightforward buffer sizes: MCSchedMode::MicroOpBufferSize MCProcResourceDesc::BufferSize These can be used to more precisely model instruction execution if desired. Disabled some misched tests temporarily. They'll be reenabled in a few commits. llvm-svn: 184032
* X86: cvtpi2ps is just an SSE instruction with MMX operands. It has no AVX ↵Benjamin Kramer2013-06-141-7/+8
| | | | | | | | equivalent. Give it the right register format so we can also emit it when AVX is enabled. llvm-svn: 183971
* X86: Make the cmov aliases work with intel syntax too.Benjamin Kramer2013-06-131-21/+25
| | | | llvm-svn: 183907
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