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* random acts of tidiness.Chris Lattner2010-11-141-10/+5
| | | | llvm-svn: 119049
* Recognise 32-bit ror-based bswap implementation used by uclibcPeter Collingbourne2010-11-131-0/+29
| | | | llvm-svn: 119007
* Support ; as asm separatorPeter Collingbourne2010-11-131-1/+1
| | | | llvm-svn: 119006
* MC: Simplify Mach-O and ELF object writer implementations.Daniel Dunbar2010-11-131-14/+14
| | | | | | - What was I thinking????? llvm-svn: 118992
* Revert r118917, which is implicated in the llvm-gcc-i386-linux-selfhost failure.Dan Gohman2010-11-131-5/+5
| | | | llvm-svn: 118954
* When the definition of an address value is in a different blockDan Gohman2010-11-121-5/+5
| | | | | | | | from the user of the address, fall back to just using the address in a register instead of bailing out of fast-isel altogether. llvm-svn: 118917
* accept lret as an alias for lretl, fixing the reopened part of PR8592Chris Lattner2010-11-122-2/+5
| | | | llvm-svn: 118916
* implement PR8592: empirically "lretq" is a "lret" with a rex.w prefix.Chris Lattner2010-11-121-0/+2
| | | | llvm-svn: 118903
* tidy up.Chris Lattner2010-11-121-3/+2
| | | | llvm-svn: 118896
* Remove possibly useful info from comment, per Chris.Dale Johannesen2010-11-121-1/+1
| | | | llvm-svn: 118865
* Remove some explicit arguments to getELFSection. This isRafael Espindola2010-11-111-1/+1
| | | | | | a leftover from the removal of isExplicit. llvm-svn: 118774
* Fix PR8211Bruno Cardoso Lopes2010-11-081-0/+6
| | | | llvm-svn: 118445
* implement aliases for div/idiv that have an explicit A register operand,Chris Lattner2010-11-061-0/+20
| | | | | | implementing rdar://8431864 llvm-svn: 118364
* add aliases for movs between seg registers and mem. There are multipleChris Lattner2010-11-061-0/+5
| | | | | | | | | | different forms of this instruction (movw/movl/movq) which we reported as being ambiguous. Since they all do the same thing, gas just picks the one with the shortest encoding. Follow its lead here. This implements rdar://8208615 llvm-svn: 118362
* move the "sh[lr]d op,op" -> "shld $1, op,op" aliases to the .td file.Chris Lattner2010-11-062-10/+18
| | | | llvm-svn: 118361
* work-in-progressChris Lattner2010-11-061-7/+6
| | | | llvm-svn: 118358
* go to great lengths to work around a GAS bug my previous patchChris Lattner2010-11-062-8/+8
| | | | | | | | | | | | | | | | exposed: GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)" even though st(0) is implicit in all other fp stack instructions. Fortunately, there is an alias for fcomip named "fcompi" and gas does accept the default argument for the alias (boggle!). As such, switch the canonical form of this instruction to "pi" instead of "ip". This makes the code generator and disassembler generate pi, avoiding the gas bug. llvm-svn: 118356
* rework the rotate-by-1 instructions to be defined like theChris Lattner2010-11-063-25/+46
| | | | | | | | | | | | | shift-by-1 instructions, where the asmstring doesn't contain the implicit 1. It turns out that a bunch of these rotate instructions were completely broken because they used 1 instead of $1. This fixes assembly mismatches on "rclb $1, %bl" and friends, where we used to generate the 3 byte form, we now generate the proper 2-byte form. llvm-svn: 118355
* change the fp comparison instructions to not have %st0 explicitlyChris Lattner2010-11-062-12/+9
| | | | | | | listed in its asm string, for consistency with the other similar instructions. llvm-svn: 118354
* move the plethora of fp stack aliases to the .td file.Chris Lattner2010-11-062-39/+48
| | | | llvm-svn: 118353
* add (and document) the ability for alias results to haveChris Lattner2010-11-062-13/+16
| | | | | | | | fixed physical registers. Start moving fp comparison aliases to the .td file (which default to using %st1 if nothing is specified). llvm-svn: 118352
* generalize alias support to allow the result of an alias toChris Lattner2010-11-062-21/+20
| | | | | | | add fixed immediate values. Move the aad and aam aliases to use this, and document it. llvm-svn: 118350
* move fnstsw aliases to .td file, fix typoChris Lattner2010-11-062-36/+6
| | | | llvm-svn: 118349
* move in/out aliases to the .td files.Chris Lattner2010-11-062-16/+16
| | | | llvm-svn: 118348
* move sldt, imul, and movabsq aliases from c++ to .td file.Chris Lattner2010-11-062-29/+18
| | | | llvm-svn: 118347
* correct suffix matching to search for s/l/t suffixes on Chris Lattner2010-11-061-33/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | floating point stack instructions instead of looking for b/w/l/q. This fixes issues where we'd accidentally match fistp to fistpl, when it is in fact an ambiguous instruction. This changes the behavior of llvm-mc to reject fstp, which was the correct fix for rdar://8456389: t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt') fstp (%rax) it also causes us to correctly reject fistp and fist, which addresses PR8528: t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl') fistp (%rax) ^ t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl') fist (%rax) ^ Thanks to Ismail Donmez for tracking down the issue here! llvm-svn: 118346
* fix a bug where we had an implicit assumption that theChris Lattner2010-11-062-27/+14
| | | | | | | | result instruction operand numbering matched the result pattern. Fixing this allows us to move the xchg/test aliases to the .td file. llvm-svn: 118334
* move the lcall/ljmp aliases to the .td file.Chris Lattner2010-11-062-33/+20
| | | | llvm-svn: 118332
* move the "movsd -> movsl" alias to the .td files, Chris Lattner2010-11-062-36/+17
| | | | | | tidy up the movsx and movzx aliases. llvm-svn: 118331
* fix some bugs in the alias support, unblocking changing of "clr" aliasesChris Lattner2010-11-062-11/+6
| | | | | | from c++ hacks to proper .td InstAlias definitions. Change them! llvm-svn: 118330
* Reimplement BuildResultOperands to be in terms of the result instruction'sChris Lattner2010-11-061-26/+13
| | | | | | | | | | | | | | | | | | operand list instead of the operand list redundantly declared on the alias or instruction. With this change, we finally remove the ins/outs list on the alias. Before: def : InstAlias<(outs GR16:$dst), (ins GR8 :$src), "movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>; After: def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>; This also makes the alias mechanism more general and powerful, which will be exploited in subsequent patches. llvm-svn: 118329
* Allow targets to specify the MachO CPUType/CPUSubtype information.Jim Grosbach2010-11-051-2/+5
| | | | llvm-svn: 118288
* When passing a huge parameter using the byval mechanism, a longDuncan Sands2010-11-041-7/+17
| | | | | | | | | sequence of loads and stores was being generated to perform the copy on the x86 targets if the parameter was less than 4 byte aligned, causing llc to use up vast amounts of memory and time. Use a "rep movs" form instead. PR7170. llvm-svn: 118260
* In the calling convention logic, ValVT is always a legal type,Duncan Sands2010-11-041-1/+1
| | | | | | | and as such can be represented by an MVT - the more complicated EVT is not needed. Use MVT for ValVT everywhere. llvm-svn: 118245
* Simplify uses of MVT and EVT. An MVT can be compared directlyDuncan Sands2010-11-031-1/+1
| | | | | | | with a SimpleValueType, while an EVT supports equality and inequality comparisons with SimpleValueType. llvm-svn: 118169
* Inside the calling convention logic LocVT is always a simpleDuncan Sands2010-11-031-24/+25
| | | | | | | | | | value type, so there is no point in passing it around using an EVT. Use the simpler MVT everywhere. Rather than trying to propagate this information maximally in all the code that using the calling convention stuff, I chose to do a mainly low impact change instead. llvm-svn: 118167
* rearrange a bit.Chris Lattner2010-11-011-50/+55
| | | | llvm-svn: 117967
* use our fancy new MnemonicAlias mechanism to remove a bunch of hacksChris Lattner2010-11-012-51/+16
| | | | | | from X86AsmParser.cpp llvm-svn: 117952
* "mov[zs]x (mem), GR16" are not ambiguous: the memChris Lattner2010-11-011-0/+6
| | | | | | must be 8 bits. Support this memory form. llvm-svn: 117902
* Implement enough of the missing instalias support to getChris Lattner2010-11-012-3/+33
| | | | | | | | | | | | | | | | | | aliases installed and working. They now work when the matched pattern and the result instruction have exactly the same operand list. This is now enough for us to define proper aliases for movzx and movsx, implementing rdar://8017633 and PR7459. Note that we do not accept instructions like: movzx 0(%rsp), %rsi GAS accepts this instruction, but it doesn't make any sense because we don't know the size of the memory operand. It could be 8/16/32 bits. llvm-svn: 117901
* make the asm matcher emitter reject instructions that have commentsChris Lattner2010-11-011-2/+2
| | | | | | | in their asmstring. Fix the two x86 "NOREX" instructions that have them. If these comments are important, the instlowering stuff can print them. llvm-svn: 117897
* reject instructions that contain a \n in their asmstring. MarkChris Lattner2010-11-011-8/+10
| | | | | | | various X86 and ARM instructions that are bitten by this as isCodeGenOnly, as they are. llvm-svn: 117884
* fix the !eq operator in tblgen to return a bit instead of an int.Chris Lattner2010-10-311-0/+3
| | | | | | | | Use this to make the X86 and ARM targets set isCodeGenOnly=1 automatically for their instructions that have Format=Pseudo, resolving a hack in tblgen. llvm-svn: 117862
* two changes: make the asmmatcher generator ignore ARM pseudos properly,Chris Lattner2010-10-312-4/+14
| | | | | | | and make it a hard error for instructions to not have an asm string. These instructions should be marked isCodeGenOnly. llvm-svn: 117861
* sketch out the planned instruction alias mechanism, add some comments aboutChris Lattner2010-10-311-0/+14
| | | | | | how the push/pop mnemonic aliases are wrong. llvm-svn: 117857
* Factorize the duplicated logic for choosing the right argumentDuncan Sands2010-10-314-56/+36
| | | | | | | calling convention out of the fast and normal ISel files, and into the calling convention TD file. llvm-svn: 117856
* Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86,Duncan Sands2010-10-311-16/+1
| | | | | | | which has the same logic specified in the CallingConv TD file. This brings FastISel in line with the standard X86 ISel. llvm-svn: 117855
* Resolve a terrible hack in tblgen: instead of hardcodingChris Lattner2010-10-301-2/+2
| | | | | | | "In32BitMode" and "In64BitMode" into tblgen, allow any predicate that inherits from AssemblerPredicate. llvm-svn: 117831
* Implement (and document!) support for MnemonicAlias's to have Requires Chris Lattner2010-10-302-14/+20
| | | | | | | | | | | directives, allowing things like this: def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>; def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>; Move the rest of the X86 MnemonicAliases over to the .td file. llvm-svn: 117830
* really zap alias.Chris Lattner2010-10-301-1/+0
| | | | llvm-svn: 117824
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