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* [ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.Chad Rosier2012-09-211-0/+4
| | | | llvm-svn: 164420
* Add comment.Chad Rosier2012-09-211-1/+2
| | | | llvm-svn: 164415
* Fix a typo in r164357Michael Liao2012-09-211-8/+8
| | | | llvm-svn: 164372
* Add missing i8 max/min/umax/umin supportMichael Liao2012-09-211-9/+44
| | | | | | - Fix PR5145 and turn on test 8-bit atomic ops llvm-svn: 164358
* Revise td of X86 atomic instructionsMichael Liao2012-09-213-218/+209
| | | | | | | - Rewirte most atomic instructions in templates for both better maintenance and future extensions, such as HLE in TSX. llvm-svn: 164357
* Re-work X86 code generation of atomic ops with spin-loopMichael Liao2012-09-205-540/+508
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Rewrite/merge pseudo-atomic instruction emitters to address the following issue: * Reduce one unnecessary load in spin-loop previously the spin-loop looks like thisMBB: newMBB: ld t1 = [bitinstr.addr] op t2 = t1, [bitinstr.val] not t3 = t2 (if Invert) mov EAX = t1 lcs dest = [bitinstr.addr], t3 [EAX is implicit] bz newMBB fallthrough -->nextMBB the 'ld' at the beginning of newMBB should be lift out of the loop as lcs (or CMPXCHG on x86) will load the current memory value into EAX. This loop is refined as: thisMBB: EAX = LOAD [MI.addr] mainMBB: t1 = OP [MI.val], EAX LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined] JNE mainMBB sinkMBB: * Remove immopc as, so far, all pseudo-atomic instructions has all-register form only, there is no immedidate operand. * Remove unnecessary attributes/modifiers in pseudo-atomic instruction td * Fix issues in PR13458 - Add comprehensive tests on atomic ops on various data types. NOTE: Some of them are turned off due to missing functionality. - Revise tests due to the new spin-loop generated. llvm-svn: 164281
* Unify the logic in SelectAtomicLoadAdd and SelectAtomicLoadArithMichael Liao2012-09-191-176/+140
| | | | | | | | | | | - Merge the processing of LOAD_ADD with other atomic load-arith operations - Separate the logic getting target constant for atomic-load-op and add an optimization for atomic-load-add on i16 with negative value - Optimize a minor case for atomic-fetch-add i16 with negative operand. Test case is revised. llvm-svn: 164243
* Remove code for setting the VEX L-bit as a function of operand size from the ↵Craig Topper2012-09-193-22/+2
| | | | | | code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. llvm-svn: 164204
* Add explicit VEX_L tags to all 256-bit instructions. This will allow us to ↵Craig Topper2012-09-193-240/+254
| | | | | | remove code from the code emitters that examined operands to set the L-bit. llvm-svn: 164202
* When creating MCAsmBackend pass the CPU string as well. In X86AsmBackendRoman Divacky2012-09-182-26/+34
| | | | | | | | | store this and use it to not emit long nops when the CPU is geode which doesnt support them. Fixes PR11212. llvm-svn: 164132
* Add some cases to x86 OptimizeCompare to handle DEC and INC, too.Jan Wen Voung2012-09-171-4/+14
| | | | | | While we are setting the earlier def to true, also make it live. llvm-svn: 164056
* LLVM_ATTRIBUTE_USED forces emission of a function. To silence unused ↵Benjamin Kramer2012-09-171-2/+2
| | | | | | function warnings use LLVM_ATTRIBUTE_UNUSED. llvm-svn: 164036
* The PMOVZXWD family of functions had patterns extends narrow vector types to ↵Nadav Rotem2012-09-161-0/+24
| | | | | | | | | | | wide vector types. It had patterns for zext-loading and extending. This commit adds patterns for loading a wide type, performing a bitcast, and extending. This is an odd pattern, but it is commonly used when writing code with intrinsics. rdar://11897677 llvm-svn: 163995
* Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.Craig Topper2012-09-151-2/+2
| | | | llvm-svn: 163974
* X86: Emitting x87 fsin/fcos for sinf/cosf is not safe without unsafe fp math.Benjamin Kramer2012-09-151-0/+2
| | | | | | This was only an issue if sse is disabled. llvm-svn: 163967
* Fix Doxygen issues:Dmitri Gribenko2012-09-141-2/+2
| | | | | | | | | | * wrap code blocks in \code ... \endcode; * refer to parameter names in paragraphs correctly (\arg is not what most people want -- it starts a new paragraph); * use \param instead of \arg to document parameters in order to be consistent with the rest of the codebase. llvm-svn: 163902
* Fix commentMichael Liao2012-09-131-1/+1
| | | | llvm-svn: 163835
* Add wider vector/integer support for PR12312Michael Liao2012-09-132-100/+103
| | | | | | | | - Enhance the fix to PR12312 to support wider integer, such as 256-bit integer. If more than 1 fully evaluated vectors are found, POR them first followed by the final PTEST. llvm-svn: 163832
* Fix the TCRETURNmi64 bug differently.Jakob Stoklund Olesen2012-09-131-2/+21
| | | | | | | | | | Add a PatFrag to match X86tcret using 6 fixed registers or less. This avoids folding loads into TCRETURNmi64 using 7 or more volatile registers. <rdar://problem/12282281> llvm-svn: 163819
* Revert r163761 "Don't fold indexed loads into TCRETURNmi64."Jakob Stoklund Olesen2012-09-133-39/+1
| | | | | | The patch caused "Wrong topological sorting" assertions. llvm-svn: 163810
* Add a new compression type to ModRM table that detects when the memory modRM ↵Craig Topper2012-09-132-0/+9
| | | | | | byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren. llvm-svn: 163774
* Don't fold indexed loads into TCRETURNmi64.Jakob Stoklund Olesen2012-09-133-1/+39
| | | | | | | | | | | | | We don't have enough GR64_TC registers when calling a varargs function with 6 arguments. Since %al holds the number of vector registers used, only %r11 is available as a scratch register. This means that addressing modes using both base and index registers can't be folded into TCRETURNmi64. <rdar://problem/12282281> llvm-svn: 163761
* Fix PR11985Michael Liao2012-09-122-15/+26
| | | | | | | | | | | - BlockAddress has no support of BA + offset form and there is no way to propagate that offset into machine operand; - Add BA + offset support and a new interface 'getTargetBlockAddress' to simplify target block address forming; - All targets are modified to use new interface and X86 backend is enhanced to support BA + offset addressing. llvm-svn: 163743
* [ms-inline asm] Make the operand size directives case insensitive.Chad Rosier2012-09-121-8/+9
| | | | llvm-svn: 163729
* Add support for AMD Geode.Roman Divacky2012-09-121-0/+1
| | | | llvm-svn: 163710
* Indentation fixes. No functional change.Craig Topper2012-09-121-8/+8
| | | | llvm-svn: 163682
* Release build: guard dump functions withManman Ren2012-09-112-2/+2
| | | | | | | | "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163339. llvm-svn: 163653
* StringSwitchify.Chad Rosier2012-09-111-8/+10
| | | | llvm-svn: 163649
* Simplify logic. No functional change intended.Chad Rosier2012-09-111-9/+8
| | | | llvm-svn: 163648
* Make a bunch of lowering helper functions static instead of member ↵Craig Topper2012-09-112-82/+56
| | | | | | functions. No functional change. llvm-svn: 163596
* Change unsigned to a uint16_t in static disassembler tables to reduce the ↵Craig Topper2012-09-112-2/+2
| | | | | | table size. llvm-svn: 163594
* Update function names to conform to guidelines. No functional change intended.Chad Rosier2012-09-107-14/+14
| | | | llvm-svn: 163561
* Revert r163556. Missed updates to tablegen files.Chad Rosier2012-09-102-4/+4
| | | | llvm-svn: 163557
* Update function names to conform to guidelines. No functional change intended.Chad Rosier2012-09-102-4/+4
| | | | llvm-svn: 163556
* Remove redundant semicolons which are null statements.Dmitri Gribenko2012-09-101-1/+1
| | | | llvm-svn: 163547
* [ms-inline asm] Pass the correct AsmVariant to the PrintAsmOperand() functionChad Rosier2012-09-102-4/+6
| | | | | | and update the printOperand() function accordingly. llvm-svn: 163544
* [ms-inline asm] Add support for .att_syntax directive.Chad Rosier2012-09-101-1/+4
| | | | llvm-svn: 163542
* Enhance PR11334 fix to support extload from v2f32/v4f32Michael Liao2012-09-103-7/+15
| | | | | | - Fix an remaining issue of PR11674 as well llvm-svn: 163528
* Add boolean simplification support from CMOVMichael Liao2012-09-101-12/+42
| | | | | | | | - If a boolean value is generated from CMOV and tested as boolean value, simplify the use of test result by referencing the original condition. RDRAND intrinisc is one of such cases. llvm-svn: 163516
* The VPSHUFB 256-bit instruction may be generated when one of input vector is ↵Elena Demikhovsky2012-09-101-4/+15
| | | | | | | | undefined or zeroinitializer. I've added the "zeroinitializer" case in this patch. llvm-svn: 163506
* Add missing space before {. No functionality change.Nick Lewycky2012-09-091-1/+1
| | | | llvm-svn: 163484
* Add instruction selection for ffloor of vectors when SSE4.1 or AVX is enabled.Craig Topper2012-09-082-20/+41
| | | | llvm-svn: 163473
* Use 256-bit alignment for constant pool value for 256-bit vector FNEG lowering.Craig Topper2012-09-081-2/+3
| | | | llvm-svn: 163463
* Add support for lowering FABS of vector types.Craig Topper2012-09-081-12/+25
| | | | llvm-svn: 163461
* Set operation action for FFLOOR to Expand for all vector types for X86. Set ↵Craig Topper2012-09-081-0/+1
| | | | | | FFLOOR of v4f32 to Expand for ARM. v2f64 was already correct. llvm-svn: 163458
* PR13754: llvm-mc/x86 crashes on .cfi directives without the % prefix for ↵Benjamin Kramer2012-09-071-5/+6
| | | | | | | | | registers. gas accepts this and it seems to be common enough to be worth supporting. This doesn't affect the parsing of reg operands outside of .cfi directives. llvm-svn: 163390
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-062-0/+4
| | | | | | No functional change. llvm-svn: 163339
* AVX2 optimization.Elena Demikhovsky2012-09-061-0/+40
| | | | | | Added generation of VPSHUB instruction for <32 x i8> vector shuffle when possible. llvm-svn: 163312
* Remove duplicated helper functionMichael Liao2012-09-061-17/+1
| | | | llvm-svn: 163295
* Use iPTR instead of i32 for extract_subvector/insert_subvector index in ↵Craig Topper2012-09-062-78/+78
| | | | | | lowering and patterns. This makes it consistent with the incoming DAG nodes from the DAG builder. llvm-svn: 163293
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