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* [X86][BtVer2] Cleanup some old FIXMEs from the model. NFCI.Simon Pilgrim2018-04-201-5/+2
| | | | llvm-svn: 330428
* [X86] Tag CLDEMOTE instruction with WriteLoad scheduling classSimon Pilgrim2018-04-201-1/+2
| | | | | | Same as other cacheline instructions llvm-svn: 330424
* [X86] Enable popcnt false dependency breaking on Silvermont and Goldmont.Craig Topper2018-04-191-2/+6
| | | | | | Silvermont and Goldmont have the same issue on popcnt as Sandy Bridge, Haswell, Broadwell, and Skylake. Believe it is fixed in Goldmont Plus. llvm-svn: 330358
* [X86][SLM] Fix typo using SandyBridge resources. Simon Pilgrim2018-04-191-2/+2
| | | | | | Luckily this was on instructions not supported on Silvermont.... llvm-svn: 330351
* [X86] Correct the scheduling data for register forms of XCHG and XADD on ↵Craig Topper2018-04-195-22/+24
| | | | | | | | | | | | Intel CPUs. The XCHG16rr/XCHG32rr/XCHG64rr instructions should be 3 uops just like XCHG8rr. I believe they're just implemented as 3 move uops with a temporary register. XADD is probably 2 moves and an add also using a temporary register. Change the latency for both from 2 cycles to 3 cycles. Only 2 of the uops are serialized in their execution, the move into the temporary and the move out of the temporary. The move from one GPR to the other should be able to go in parallel with this if there are ALU resources available. llvm-svn: 330349
* [X86] Merge some MMX instregexSimon Pilgrim2018-04-195-269/+88
| | | | | | There's a lot more but I'd prefer focussing on removing unnecessary InstRWs first. llvm-svn: 330347
* [X86][BtVer2] Remove SSE4A EXTRQ/EXTRQI InstRW overrides.Simon Pilgrim2018-04-191-4/+0
| | | | | | These are already handled identically by WriteALU. llvm-svn: 330332
* Lowering x86 adds/addus/subs/subus intrinsics (llvm part)Alexander Ivchenko2018-04-192-40/+89
| | | | | | | | | | | | | This is the patch that lowers x86 intrinsics to native IR in order to enable optimizations. The patch also includes folding of previously missing saturation patterns so that IR emits the same machine instructions as the intrinsics. Patch by tkrupa Differential Revision: https://reviews.llvm.org/D44785 llvm-svn: 330322
* [X86][FMA] Remove FMA reg-reg InstRW scheduler overrides.Simon Pilgrim2018-04-194-25/+1
| | | | | | These are all already handled identically by WriteFMA. llvm-svn: 330319
* [X86][BtVer2] Remove 128-bit F16C InstRW overrides.Simon Pilgrim2018-04-191-10/+0
| | | | | | These are already handled identically by WriteCvtF2F. llvm-svn: 330318
* [X86] Scrub scheduling information for MUL/IMUL on Intel CPUs.Craig Topper2018-04-195-35/+81
| | | | | | This removes a bunch of unnecessary InstRW overrides. It also cleans up the missing information from the Sandy Bridge model. Other fixes to other models. llvm-svn: 330308
* Fix data race in X86FloatingPoint.cpp ASSERT_SORTEDBob Haarman2018-04-181-7/+8
| | | | | | | | | | | | | | | | | | | | | Summary: ASSERT_SORTED checks if a table is sorted, and uses a boolean to prevent the check from being run again if it was earlier determined that the table is in fact sorted. Unsynchronized reads and writes of that boolean triggered ThreadSanitizer's data race detection. This change rewrites the code to use std::atomic<bool> instead. Fixes PR36922. Reviewers: rnk Reviewed By: rnk Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D45742 llvm-svn: 330301
* [X86] Correct the Defs, Uses, hasSideEffects, mayLoad, mayStore for XCHG and ↵Craig Topper2018-04-183-35/+52
| | | | | | | | XADD instructions. I don't think we emit any of these from codegen except for using XCHG16ar as 2 byte NOP. llvm-svn: 330298
* [X86] Fix the Uses/Defs,mayLoad,mayStore,hasSideEffects flags for the ↵Craig Topper2018-04-181-6/+13
| | | | | | | | CMPXCHG instructions. The compiler only emits the locked version of these which use different instruction definitions. The versions fixed here are only used by the assembler/disassembler. llvm-svn: 330287
* [x86] Switch EFLAGS copy lowering to use reg-reg form of testing forChandler Carruth2018-04-181-1/+1
| | | | | | | | | | | | | | | | a zero register. Previously I tried this and saw LLVM unable to transform this to fold with memory operands such as spill slot rematerialization. However, it clearly works as shown in this patch. We turn these into `cmpb $0, <mem>` when useful for folding a memory operand without issue. This form has no disadvantage compared to `testb $-1, <mem>`. So overall, this is likely no worse and may be slightly smaller in some cases due to the `testb %reg, %reg` form. Differential Revision: https://reviews.llvm.org/D45475 llvm-svn: 330269
* [x86] Fix PR37100 by teaching the EFLAGS copy lowering to rewrite usesChandler Carruth2018-04-181-82/+125
| | | | | | | | | | | | | | | | | | | | | | across basic blocks in the limited cases where it is very straight forward to do so. This will also be useful for other places where we do some limited EFLAGS propagation across CFG edges and need to handle copy rewrites afterward. I think this is rapidly approaching the maximum we can and should be doing here. Everything else begins to require either heroic analysis to prove how to do PHI insertion manually, or somehow managing arbitrary PHI-ing of EFLAGS with general PHI insertion. Neither of these seem at all promising so if those cases come up, we'll almost certainly need to rewrite the parts of LLVM that produce those patterns. We do now require dominator trees in order to reliably diagnose patterns that would require PHI nodes. This is a bit unfortunate but it seems better than the completely mysterious crash we would get otherwise. Differential Revision: https://reviews.llvm.org/D45673 llvm-svn: 330264
* [X86][Broadwell] Remove some unnecessary InstRW overrides and add some FIXMEs.Craig Topper2018-04-181-43/+8
| | | | llvm-svn: 330241
* [X86] Give CMOV 2 cycle latency on SLM.Craig Topper2018-04-181-1/+1
| | | | llvm-svn: 330239
* [X86] Don't crash on bad operand modifiers in inline assemblyCraig Topper2018-04-181-0/+6
| | | | | | | | | | | | | | Summary: Previously if a modifer was placed on a non-GPR register class we would hit an assert or crash. Reviewers: echristo Reviewed By: echristo Subscribers: eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D45751 llvm-svn: 330238
* [XRay] Typed event logging intrinsicKeith Wyss2018-04-173-352/+912
| | | | | | | | | | | | | | | | | | | | | Summary: Add an LLVM intrinsic for type discriminated event logging with XRay. Similar to the existing intrinsic for custom events, but also accepts a type tag argument to allow plugins to be aware of different types and semantically interpret logged events they know about without choking on those they don't. Relies on a symbol defined in compiler-rt patch D43668. I may wait to submit before I can see demo everything working together including a still to come clang patch. Reviewers: dberris, pelikan, eizan, rSerge, timshen Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45633 llvm-svn: 330219
* [X86] Add separate scheduling class for PSADBW instruction.Craig Topper2018-04-1713-22/+18
| | | | llvm-svn: 330204
* [X86] Remove unnecessary InstRW overrides. Add somes FIXMEs/TODOs.Craig Topper2018-04-175-98/+17
| | | | llvm-svn: 330203
* [X86] Add FP comparison scheduler classesSimon Pilgrim2018-04-1713-315/+105
| | | | | | | | Split VCMP/VMAX/VMIN instructions off to WriteFCmp and VCOMIS instructions off to WriteFCom instead of assuming they match WriteFAdd Differential Revision: https://reviews.llvm.org/D45656 llvm-svn: 330179
* [X86] Introduce archs: goldmont-plus & tremontGabor Buella2018-04-162-13/+43
| | | | | | | | | | | | | | | Using Goldmont's cost tables for these two upcoming atom archs. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45612 llvm-svn: 330109
* [X86] Use uint32_t instead of unsigned in GetLo32XForm for readability. NFCCraig Topper2018-04-151-1/+1
| | | | | | GetLo8XForm right next to it uses uint8_t so uint32_t is consistent. llvm-svn: 330104
* [X86][MMX] Set PAVG/PHADD/PMIN/PMAX/PSIGN instructions to use same scheduler ↵Simon Pilgrim2018-04-141-12/+12
| | | | | | classes as SSE/AVX llvm-svn: 330085
* [NFC] fix trivial typos in document and commentsHiroshi Inoue2018-04-141-1/+1
| | | | | | "not not" -> "not" etc llvm-svn: 330083
* [X86] Add the bizarro movsww and movzww mnemonics for the disassembler.Craig Topper2018-04-131-0/+20
| | | | | | | | The destination size of the movzx/movsx instruction is controlled by the normal operand size mechanisms. Only the input type is fixed. This means that a 0x66 prefix on the encoding for zext/sext 16->32 should really produce a 16->16 instruction. Functionally this is equivalent to a GR16->GR16 move since bits 16 and above will be preserved. So nothing is actually extended. llvm-svn: 330078
* MachO: trap unreachable instructionsTim Northover2018-04-131-1/+2
| | | | | | | Debugability is more important than saving 4 bytes to let us to fall through to nonense. llvm-svn: 330073
* [X86] Remove remaining itinerary support from instructions and target (PR37093)Simon Pilgrim2018-04-133-13/+0
| | | | llvm-svn: 330035
* [X86] Generalize X86FixupLEAs to work with TargetSchedModelSimon Pilgrim2018-04-131-3/+4
| | | | | | Similar to rL329834, don't rely on itinerary scheduler model to determine latencies for LEA thresholds, use the generic TargetSchedModel::computeInstrLatency call. llvm-svn: 330030
* Remove comment reference to itineraries. NFCI.Simon Pilgrim2018-04-131-1/+1
| | | | llvm-svn: 330025
* [X86][AVX512] UNPCKL/H PS and PD should be scheduled with WriteFShuffle not ↵Simon Pilgrim2018-04-131-2/+2
| | | | | | WriteFAdd llvm-svn: 330023
* [X86] Remove remaining OpndItins/SizeItins from all instruction defs (PR37093)Simon Pilgrim2018-04-132-1715/+1301
| | | | llvm-svn: 330022
* Remove comment references to itineraries. NFCI.Simon Pilgrim2018-04-133-4/+4
| | | | llvm-svn: 330021
* Remove out of data comment. NFCI.Simon Pilgrim2018-04-131-2/+1
| | | | llvm-svn: 330019
* [X86] Remove OpndItins/SizeItins from all sse instruction defs (PR37093)Simon Pilgrim2018-04-132-622/+566
| | | | llvm-svn: 330013
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-04-131-1/+1
| | | | | | "the the" -> "the", "we we" -> "we", etc llvm-svn: 330006
* [X86] Introduce cldemote instructionGabor Buella2018-04-134-0/+11
| | | | | | | | | | | | | | Hint to hardware to move the cache line containing the address to a more distant level of the cache without writing back to memory. Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45256 llvm-svn: 329992
* [X86] Remove the pmuldq/pmuldq intrinsics and replace with native IR.Craig Topper2018-04-131-18/+0
| | | | | | | | This completes the work started in r329604 and r329605 when we changed clang to no longer use the intrinsics. We lost some InstCombine SimplifyDemandedBit optimizations through this change as we aren't able to fold 'and', bitcast, shuffle very well. llvm-svn: 329990
* [X86] Remove unused MoveLoadStoreItins/ShiftOpndItins schedule class wrappers.Simon Pilgrim2018-04-122-36/+14
| | | | | | Was being used to move around empty/unused itineraries... llvm-svn: 329970
* [X86] Remove x86 InstrItinClass entries (PR37093)Simon Pilgrim2018-04-123-241/+94
| | | | | | This removes the last of the x86 schedule itineraries, I'm intending to cleanup the remaining uses of NoItinerary/OpndItins/etc. before resolving PR37093. llvm-svn: 329967
* [X86] Remove InstrItinClass entries from all x86 instruction defs (PR37093)Simon Pilgrim2018-04-123-318/+284
| | | | llvm-svn: 329953
* [X86] Remove InstrItinClass entries from SSE/AVX instructions defs (PR37093)Simon Pilgrim2018-04-122-521/+498
| | | | llvm-svn: 329945
* [X86] Remove explicit SSE/AVX schedule itineraries from defs (PR37093)Simon Pilgrim2018-04-123-526/+463
| | | | llvm-svn: 329940
* [X86] Remove remaining gpr schedule itineraries (PR37093)Simon Pilgrim2018-04-124-353/+226
| | | | llvm-svn: 329938
* [X86] Introduce LLVM wbinvd intrinsicGabor Buella2018-04-121-1/+1
| | | | | | | | | | | | A previously missing intrinsic for an old instruction. Reviewers: craig.topper, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45312 llvm-svn: 329936
* [X86] Remove gpr shift/extension schedule itineraries (PR37093)Simon Pilgrim2018-04-123-343/+270
| | | | llvm-svn: 329933
* [X86] Remove AES/CLMUL/CRC32/LDDQU/MOVNT/POPCNT/SHA schedule itineraries ↵Simon Pilgrim2018-04-124-100/+70
| | | | | | (PR37093) llvm-svn: 329912
* [X86] Remove remaining system/special schedule itineraries (PR37093)Simon Pilgrim2018-04-125-540/+381
| | | | llvm-svn: 329906
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