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* [asan] Add a flag to control asm instrumentation.Evgeniy Stepanov2014-05-071-1/+8
| | | | | | With this change, asm instrumentation is disabled by default. llvm-svn: 208167
* [X86] Improve the lowering of BITCAST dag nodes from type f64 to type v2i32 ↵Andrea Di Biagio2014-05-061-1/+41
| | | | | | | | | | | | | | | | | | | | (and vice versa). Before this patch, the backend always emitted a store+load sequence to bitconvert from f64 to i64 the input operand of a ISD::BITCAST dag node that performed a bitconvert from type MVT::f64 to type MVT::v2i32. The resulting i64 node was then used to build a v2i32 vector. With this patch, the backend now produces a cheaper SCALAR_TO_VECTOR from MVT::f64 to MVT::v2f64. That SCALAR_TO_VECTOR is then followed by a "free" bitcast to type MVT::v4i32. The elements of the resulting v4i32 are then extracted to build a v2i32 vector (which is illegal and therefore promoted to MVT::v2i64). This is in general cheaper than emitting a stack store+load sequence to bitconvert the operand from type f64 to type i64. llvm-svn: 208107
* Implememting named register intrinsicsRenato Golin2014-05-062-0/+15
| | | | | | | | | | | This patch implements the infrastructure to use named register constructs in programs that need access to specific registers (bare metal, kernels, etc). So far, only the stack pointer is supported as a technology preview, but as it is, the intrinsic can already support all non-allocatable registers from any architecture. llvm-svn: 208104
* Use X86 memory operand enums instead of hardcoding.Craig Topper2014-05-061-16/+20
| | | | llvm-svn: 208064
* Fix i128 div/mod on mingw64Reid Kleckner2014-05-062-0/+72
| | | | | | | | | | The Win64 docs are very clear that anything larger than 8 bytes is passed by reference, and GCC MinGW64 honors that for __modti3 and friends. Patch by Jameson Nash! llvm-svn: 208029
* Revert "Optimize shufflevector that copies an i64/f64 and zeros the rest."Filipe Cabecinhas2014-05-051-21/+12
| | | | | | This reverts commit 207992. I misread the phab number on the LGTM. llvm-svn: 207993
* Optimize shufflevector that copies an i64/f64 and zeros the rest.Filipe Cabecinhas2014-05-051-12/+21
| | | | | | | | | | | | | | Summary: Also ran clang-format on the function. The code added is the last else if block. Reviewers: nadav, craig.topper Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3518 llvm-svn: 207992
* AVX-512: minor change in rndscale intrinsicElena Demikhovsky2014-05-041-2/+11
| | | | llvm-svn: 207937
* X86: further range-loopify AsmPrinterSaleem Abdulrasool2014-05-041-18/+16
| | | | | | Use more range loops in the X86AsmPrinter. NFC. llvm-svn: 207928
* X86: remove X86COFFMachineModuleInfoSaleem Abdulrasool2014-05-044-82/+0
| | | | | | Remove dead code. This is vestigial after r98384. llvm-svn: 207927
* X86: repair export compatibility with MinGW/cygwinSaleem Abdulrasool2014-05-041-1/+6
| | | | | | | | | | | | | | Both MinGW and cygwin (i686) construct export directives without the global leader prefix. This is mostly due to the fact that they use GNU ld which does not correctly handle the export directive. This apparently has been been broken for a while. However, this was recently reported as being broken by mingwandroid and diorcety of the msys2 project. Remove the global leader prefix if targeting MinGW or cygwin, otherwise, retain the global leader prefix. Add an explicit test for cygwin's behaviour of export directives. llvm-svn: 207926
* X86: refactor export directive generationSaleem Abdulrasool2014-05-042-22/+27
| | | | | | | | | Create a helper function to generate the export directive. This was previously duplicated inline to handle export directives for variables and functions. This also enables the use of range-based iterators for the generation of the directive rather than the traditional loops. NFC. llvm-svn: 207925
* Fix pr19645.Rafael Espindola2014-05-031-1/+1
| | | | | | | | | | | | | | | | The fix itself is fairly simple: move getAccessVariant to MCValue so that we replace the old weak expression evaluation with the far more general EvaluateAsRelocatable. This then requires that EvaluateAsRelocatable stop when it finds a non trivial reference kind. And that in turn requires the ELF writer to look harder for weak references. Last but not least, this found a case where we were being bug by bug compatible with gas and accepting an invalid input. I reported pr19647 to track it. llvm-svn: 207920
* Add a description for AMD's bdver4 (aka Excavator).Benjamin Kramer2014-05-021-0/+7
| | | | | | This is just bdver3 + AVX2 + BMI2. llvm-svn: 207847
* Restore condition incorrectly changed in r96289 to the older state.Joerg Sonnenberger2014-04-301-1/+1
| | | | llvm-svn: 207716
* [X86] Never hoist the shift value of a shift instruction.Michael Zolotukhin2014-04-301-3/+7
| | | | | | | | | | | There is no need to check if we want to hoist the immediate value of an shift instruction. Simply return TCC_Free right away. This change is like r206101, but for X86. rdar://problem/16190769 llvm-svn: 207692
* [asan] Disable asm instrumentation on unsupported platforms.Evgeniy Stepanov2014-04-301-3/+6
| | | | | | | | | Only emit calls to compiler-rt asm routines on platforms where they are present (currently limited to linux i386/x86_64). Patch by Yuri Gorshenin. llvm-svn: 207651
* Use makeArrayRef insted of calling ArrayRef<T> constructor directly. I ↵Craig Topper2014-04-301-5/+4
| | | | | | introduced most of these recently. llvm-svn: 207616
* Implement X86 code generation for musttailReid Kleckner2014-04-291-45/+50
| | | | | | | | | | | | | | | | | | Currently, musttail codegen is relying on sibcall optimization, and reporting a fatal error if fails. Sibcall optimization fails when stack arguments need to be modified, which is insufficient for musttail. The logic for moving arguments in memory safely is already implemented for GuaranteedTailCallOpt. This change merely arranges for musttail calls to use it. No functional change for GuaranteedTailCallOpt. Reviewers: espindola Differential Revision: http://reviews.llvm.org/D3493 llvm-svn: 207598
* X86: emit hidden stubs into a proper non_lazy_symbol_pointer section.Tim Northover2014-04-291-31/+35
| | | | | | rdar://problem/16660411 llvm-svn: 207518
* AVX-512: optimized a shuffle pattern to VINSERTI64x4.Elena Demikhovsky2014-04-292-0/+44
| | | | | | Added intrinsics for VPERMT2PS/PD/D/Q instructions. llvm-svn: 207513
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-1/+1
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. llvm-svn: 207511
* None of these targets actually define their own CFI_INSTRUCTIONEric Christopher2014-04-291-6/+7
| | | | | | | opcode so there's no reason to use the target namespace for it rather than TargetOpcode. llvm-svn: 207475
* Fix 80-columns, tab characters, and comments.Eric Christopher2014-04-291-18/+20
| | | | llvm-svn: 207472
* [X86] Add more details in the comments of ↵Quentin Colombet2014-04-281-2/+16
| | | | | | X86TargetLowering::getScalingFactorCost. llvm-svn: 207432
* Fix gcc -Wsign-compare warning in X86DisassemblerTables.cpp.Patrik Hagglund2014-04-284-17/+15
| | | | | | | | | | X86_MAX_OPERANDS is changed to unsigned. Also, add range-based for loops for affected loops. This in turn needed an ArrayRef instead of a pointer-to-array in InternalInstruction. llvm-svn: 207413
* Convert more SelectionDAG functions to use ArrayRef.Craig Topper2014-04-281-2/+2
| | | | llvm-svn: 207397
* [C++] Use 'nullptr'.Craig Topper2014-04-2810-15/+16
| | | | llvm-svn: 207394
* Convert one last signature of getNode to take an ArrayRef of SDUse.Craig Topper2014-04-271-1/+2
| | | | llvm-svn: 207376
* Convert SelectionDAG::getMergeValues to use ArrayRef.Craig Topper2014-04-272-10/+10
| | | | llvm-svn: 207374
* X86TTI: Adjust sdiv cost now that we can lower it on plain SSE2.Benjamin Kramer2014-04-271-0/+5
| | | | | | | Includes a fix for a horrible typo that caused all SDIV costs to be slightly off :) llvm-svn: 207371
* X86: If SSE4.1 is missing lower SMUL_LOHI of v4i32 to pmuludq and fix up the ↵Benjamin Kramer2014-04-271-2/+17
| | | | | | | | high parts. This is more expensive than pmuldq but still cheaper than scalarizing the whole thing. llvm-svn: 207370
* MC: create X86WinCOFFStreamer for target specific behaviourSaleem Abdulrasool2014-04-274-1/+62
| | | | | | | | | | This introduces a target specific streamer, X86WinCOFFStreamer, which handles the target specific behaviour (e.g. WinEH). This is mostly to ensure that differences between ARM and X86 remain disjoint and do not accidentally cross boundaries. This is the final staging change for enabling object emission for Windows on ARM. llvm-svn: 207344
* Convert getMemIntrinsicNode to take ArrayRef of SDValue instead of pointer ↵Craig Topper2014-04-261-20/+11
| | | | | | and size. llvm-svn: 207329
* Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>.Craig Topper2014-04-263-107/+76
| | | | llvm-svn: 207327
* Print X86ISD::PMULDQ nodes properly in debug output.Benjamin Kramer2014-04-261-0/+1
| | | | llvm-svn: 207322
* X86TTI: i16/i32 vector div with a constant (splat) divisor are reasonably ↵Benjamin Kramer2014-04-261-0/+19
| | | | | | | | cheap now. Turn vectorization back on. llvm-svn: 207320
* X86: Lower SMUL_LOHI of v4i32 to pmuldq when SSE4.1 is available.Benjamin Kramer2014-04-264-14/+56
| | | | llvm-svn: 207318
* X86: Add patterns for MULHU/MULHS of v8i16 and v16i16.Benjamin Kramer2014-04-262-4/+18
| | | | | | | This gets us pretty code for divs of i16 vectors. Turn the existing intrinsics into the corresponding nodes. llvm-svn: 207317
* Rip out X86-specific vector SDIV lowering, make the corresponding ↵Benjamin Kramer2014-04-261-64/+0
| | | | | | DAGCombiner transform work on vectors. llvm-svn: 207316
* X86: Custom lower v4i32 UMUL_LOHI into 2 pmuludqs.Benjamin Kramer2014-04-261-0/+37
| | | | | | Test will follow soon. llvm-svn: 207314
* [X86] Implement TargetLowering::getScalingFactorCost hook.Quentin Colombet2014-04-262-0/+19
| | | | | | | | | Scaling factors are not free on X86 because every "complex" addressing mode breaks the related instruction into 2 allocations instead of 1. <rdar://problem/16730541> llvm-svn: 207301
* Optimization for certain shufflevector by using insertps.Filipe Cabecinhas2014-04-251-0/+104
| | | | | | | | | | | | | | | | | | | | Summary: If we're doing a v4f32/v4i32 shuffle on x86 with SSE4.1, we can lower certain shufflevectors to an insertps instruction: When most of the shufflevector result's elements come from one vector (and keep their index), and one element comes from another vector or a memory operand. Added tests for insertps optimizations on shufflevector. Added support and tests for v4i32 vector optimization. Reviewers: nadav Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3475 llvm-svn: 207291
* X86: convert object streamer selection to a switchSaleem Abdulrasool2014-04-251-5/+8
| | | | | | | | | | | Change the object streamer selection to a switch from a series of if conditions. Rather than defaulting to ELF, require that an ELF format is requested. The Windows/!ELF is maintained as MachO would have been selected first and will still provide a MachO format. Add an assertion that if COFF is requested that the target platform is Windows as only WinCOFF object emission is currently supported. llvm-svn: 207200
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-2526-250/+262
| | | | llvm-svn: 207197
* X86: Don't transform shifts into ands when the sign bit is tested.Benjamin Kramer2014-04-241-1/+2
| | | | | | Should unbreak MultiSource/Benchmarks/mediabench/g721/g721encode/encode. llvm-svn: 207145
* Add 'musttail' marker to call instructionsReid Kleckner2014-04-241-0/+4
| | | | | | | | | | | | This is similar to the 'tail' marker, except that it guarantees that tail call optimization will occur. It also comes with convervative IR verification rules that ensure that tail call optimization is possible. Reviewers: nicholas Differential Revision: http://llvm-reviews.chandlerc.com/D3240 llvm-svn: 207143
* [X86] Add support for Read Time Stamp Counter x86 builtin intrinsics.Andrea Di Biagio2014-04-244-33/+104
| | | | | | | | | | | | | | This patch: - Adds two new X86 builtin intrinsics ('int_x86_rdtsc' and 'int_x86_rdtscp') as GCCBuiltin intrinsics; - Teaches the backend how to lower the two new builtins; - Introduces a common function to lower READCYCLECOUNTER dag nodes and the two new rdtsc/rdtscp intrinsics; - Improves (and extends) the existing x86 test 'rdtsc.ll'; now test 'rdtsc.ll' correctly verifies that both READCYCLECOUNTER and the two new intrinsics work fine for both 64bit and 32bit Subtargets. llvm-svn: 207127
* Spread some const around for non-mutating uses of MCSymbolData.David Blaikie2014-04-241-8/+9
| | | | | | | | I discovered this const-hole while attempting to coalesnce the Symbol and SymbolMap data structures. There's some pending issues with that, but I figured this change was easy to flush early. llvm-svn: 207124
* [asan] Use MCInstrInfo in inline asm instrumentation.Evgeniy Stepanov2014-04-243-26/+17
| | | | | | Patch by Yuri Gorshenin. llvm-svn: 207115
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