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* [AVX512] Remove masked store intrinsics. Clang now emits generic masked ↵Craig Topper2016-05-311-30/+0
| | | | | | | | store intrinsics instead. The intrinsics will be autoupgraded to the same generic masked stores. llvm-svn: 271245
* X86: permit using SjLj EH on x86 targets as an optionSaleem Abdulrasool2016-05-313-1/+277
| | | | | | | | | | | This adds support to the backed to actually support SjLj EH as an exception model. This is *NOT* the default model, and requires explicitly opting into it from the frontend. GCC supports this model and for MinGW can still be enabled via the `--using-sjlj-exceptions` options. Addresses PR27749! llvm-svn: 271244
* [X86] Remove SSE/AVX unaligned store intrinsics as clang no longer uses ↵Craig Topper2016-05-301-29/+0
| | | | | | them. Auto upgrade to native unaligned store instructions. llvm-svn: 271236
* Fix a crash when producing COFF.Rafael Espindola2016-05-301-0/+2
| | | | llvm-svn: 271229
* Move RelaxELFRel out to llvm-mc.Rafael Espindola2016-05-291-6/+0
| | | | llvm-svn: 271160
* [X86][SSE] (Reapplied) Replace (V)PMOVSX and (V)PMOVZX integer extension ↵Simon Pilgrim2016-05-281-18/+0
| | | | | | | | | | | | intrinsics with generic IR (llvm) This patch removes the llvm intrinsics VPMOVSX and (V)PMOVZX sign/zero extension intrinsics and auto-upgrades to SEXT/ZEXT calls instead. We already did this for SSE41 PMOVSX sometime ago so much of that implementation can be reused. Reapplied now that the the companion patch (D20684) removes/auto-upgrade the clang intrinsics has been committed. Differential Revision: http://reviews.llvm.org/D20686 llvm-svn: 271131
* Fix production of R_X86_64_GOTPCRELX/R_X86_64_REX_GOTPCRELX.Rafael Espindola2016-05-285-31/+70
| | | | | | | | We were producing R_X86_64_GOTPCRELX for invalid instructions and sometimes producing R_X86_64_GOTPCRELX instead of R_X86_64_REX_GOTPCRELX. llvm-svn: 271118
* [x86] avoid printing unnecessary sign bits of hex immediates in asm comments ↵Sanjay Patel2016-05-281-4/+13
| | | | | | | | | | | (PR20347) It would be better to check the valid/expected size of the immediate operand, but this is generally better than what we print right now. Differential Revision: http://reviews.llvm.org/D20385 llvm-svn: 271114
* [X86] Try to zero elts when lowering 256-bit shuffle with PSHUFB.Ahmed Bougacha2016-05-281-35/+66
| | | | | | | | Otherwise we fallback to a blend of PSHUFBs later on. Differential Revision: http://reviews.llvm.org/D19661 llvm-svn: 271113
* Simplify and clang-format a table.Rafael Espindola2016-05-281-5/+5
| | | | llvm-svn: 271112
* [X86] Detect SAD patterns and emit psadbw instructions.Michael Kuperstein2016-05-271-0/+140
| | | | | | | | This recommits r267649 with a fix for PR27539. Differential Revision: http://reviews.llvm.org/D20598 llvm-svn: 271033
* [X86] Clarify PSHUFB+blend lowering function name. NFC.Ahmed Bougacha2016-05-271-9/+11
| | | | | | Also guard against v32i8 users. llvm-svn: 271024
* Revert: r270973 - [X86][SSE] Replace (V)PMOVSX and (V)PMOVZX integer ↵Simon Pilgrim2016-05-271-0/+18
| | | | | | extension intrinsics with generic IR (llvm) llvm-svn: 270976
* [X86][SSE] Replace (V)PMOVSX and (V)PMOVZX integer extension intrinsics with ↵Simon Pilgrim2016-05-271-18/+0
| | | | | | | | | | | | generic IR (llvm) This patch removes the llvm intrinsics VPMOVSX and (V)PMOVZX sign/zero extension intrinsics and auto-upgrades to SEXT/ZEXT calls instead. We already did this for SSE41 PMOVSX sometime ago so much of that implementation can be reused. A companion patch (D20684) removes/auto-upgrade the clang intrinsics. Differential Revision: http://reviews.llvm.org/D20686 llvm-svn: 270973
* [X86][SSE] When lowering a 256-bit shuffle as PMOVZX, reduce the input ↵Simon Pilgrim2016-05-261-1/+7
| | | | | | | | vector to the lower 128-bit subvector. Most often as not this is what it started out as, the extraction is zero-cost on AVX and the PMOVZX/PMOVSX folding logic is based around 128-bit loads. llvm-svn: 270858
* Use shouldAssumeDSOLocal on AArch64.Rafael Espindola2016-05-261-43/+1
| | | | | | This reduces code duplication and now AArch64 also handles PIE. llvm-svn: 270844
* [AVX512] Fix intrinsic cmp{sd|ss} lowering.Igor Breger2016-05-261-3/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D20615 llvm-svn: 270843
* Simplify std::all_of/any_of predicates by using llvm::all_of/any_of. NFCI.Simon Pilgrim2016-05-251-7/+5
| | | | llvm-svn: 270753
* Fix shouldAssumeDSOLocal for private linkage.Rafael Espindola2016-05-251-1/+1
| | | | llvm-svn: 270746
* [x86] avoid code explosion from LoopVectorizer for gather loop (PR27826) Sanjay Patel2016-05-251-2/+10
| | | | | | | | | | | | | | By making pointer extraction from a vector more expensive in the cost model, we avoid the vectorization of a loop that is very likely to be memory-bound: https://llvm.org/bugs/show_bug.cgi?id=27826 There are still bugs related to this, so we may need a more general solution to avoid vectorizing obviously memory-bound loops when we don't have HW gather support. Differential Revision: http://reviews.llvm.org/D20601 llvm-svn: 270729
* [x86, AVX] allow explicit calls to VZERO* to modify state in ↵Sanjay Patel2016-05-251-6/+7
| | | | | | | | | | VZeroUpperInserter pass (PR27823) As noted in the review, there are still problems, so this doesn't the bug completely. Differential Revision: http://reviews.llvm.org/D20529 llvm-svn: 270718
* [X86][SSE] Replace (V)CVTDQ2PD(Y) and (V)CVTPS2PD(Y) lossless conversion ↵Simon Pilgrim2016-05-251-29/+15
| | | | | | | | | | intrinsics with generic IR Followup to D20528 clang patch, this removes the (V)CVTDQ2PD(Y) and (V)CVTPS2PD(Y) llvm intrinsics and auto-upgrades to sitofp/fpext instead. Differential Revision: http://reviews.llvm.org/D20568 llvm-svn: 270678
* [X86] Remove the llvm.x86.sse2.storel.dq intrinsic. It hasn't been used in a ↵Craig Topper2016-05-251-7/+0
| | | | | | long time. llvm-svn: 270677
* [llvm][AVX512][intrinsics] Fix vperm{b|w|d|q|ps|pd} intrinsics. Index is ↵Igor Breger2016-05-242-15/+39
| | | | | | | | second argument to buildin function but it is first instruction operand. Differential Revision: http://reviews.llvm.org/D20515 llvm-svn: 270548
* [CostModel][X86][XOP] Added XOP costmodel for BITREVERSE Simon Pilgrim2016-05-242-1/+49
| | | | | | Now that we have a nice fast VPPERM solution. Added framework for future intrinsic costs as well. llvm-svn: 270537
* fix typo; NFCSanjay Patel2016-05-231-1/+1
| | | | llvm-svn: 270469
* use range-loop; NFCISanjay Patel2016-05-231-4/+2
| | | | llvm-svn: 270467
* Removing a switch statement that contains only a default label; NFC.Aaron Ballman2016-05-231-3/+1
| | | | llvm-svn: 270444
* [X86] Use instruction aliases to replace custom asm parser code for ↵Craig Topper2016-05-233-51/+53
| | | | | | optimizing moves to use 2 byte VEX prefix. llvm-svn: 270394
* [AVX512] Add patterns to implement stores of extracts of least signficant ↵Craig Topper2016-05-221-0/+123
| | | | | | | | subvectors using XMM or YMM stores instead of the vector extract instructions. Similar is already done for AVX and we had lost it going to AVX512VL. llvm-svn: 270383
* [x86, AVX] don't add a vzeroupper if that's what the code is already doing ↵Sanjay Patel2016-05-221-0/+6
| | | | | | | | | | | | | | | (PR27823) This isn't the complete fix, but it handles the trivial examples of duplicate vzero* ops in PR27823: https://llvm.org/bugs/show_bug.cgi?id=27823 ...and amusingly, the bogus cases already exist as regression tests, so let's take this baby step. We'll need to do more in the general case where there's legitimate AVX usage in the function + there's already a vzero in the code. Differential Revision: http://reviews.llvm.org/D20477 llvm-svn: 270378
* [AVX512] Implement missing patterns for any_extend load lowering.Igor Breger2016-05-222-55/+88
| | | | | | Differential Revision: http://reviews.llvm.org/D20513 llvm-svn: 270357
* [AVX512] The AVX512 file only need subtract_subvector index 0 patterns where ↵Craig Topper2016-05-221-15/+35
| | | | | | the source is 512-bits. The 256-bit source patterns were redundant with AVX. llvm-svn: 270356
* [AVX512] Add an AddedComplexity line to the 512-bit insert_subvector undef ↵Craig Topper2016-05-221-0/+2
| | | | | | index 0 patterns. This gives them higher priority than the memory patterns. This matches AVX1/2. llvm-svn: 270355
* [AVX512] Change the AddedComplexity on some patterns to match their AVX/SSE ↵Craig Topper2016-05-221-9/+13
| | | | | | equivalents. This helps group them close together in the isel tables and enable table compression. llvm-svn: 270354
* [AVX512] Add a couple patterns to fix some cases where two vector mask ↵Craig Topper2016-05-221-0/+11
| | | | | | inversions could appear in a row. llvm-svn: 270344
* [AVX512] Remove seemingly unnecessary AddedComplexity adjustment.Craig Topper2016-05-221-2/+0
| | | | llvm-svn: 270343
* [X86] Remove unnecessary alignment check on patterns that use VEXTRACTF128 ↵Craig Topper2016-05-211-8/+8
| | | | | | for integer types when only AVX1 is supported. llvm-svn: 270335
* [AVX512] Add patterns for extracting subvectors and storing to memory.Craig Topper2016-05-212-10/+15
| | | | llvm-svn: 270334
* [AVX512] Capitalize the Z in VEXTRACTPSzmr. Lowercase z has been primarily ↵Craig Topper2016-05-211-2/+2
| | | | | | used to indicating the zero masking behavior which is not the case here. NFC llvm-svn: 270333
* [AVX512] Rename vector extract instructions so 'mr' intead of 'rm' to ↵Craig Topper2016-05-211-2/+2
| | | | | | reflect the fact that memory is the destination. llvm-svn: 270332
* [AVX512] Fix copy/paste mistake a I made in a comment.Craig Topper2016-05-211-1/+1
| | | | llvm-svn: 270331
* [Clang][AVX512][intrinsics] Fix rcp and sqrt intrinsics.Michael Zuckerman2016-05-214-7/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D20438 llvm-svn: 270322
* [Clang][AVX512][intrinsics] Fix vscalef intrinsics.Michael Zuckerman2016-05-215-8/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D20324 llvm-svn: 270321
* [AVX512] Add patterns for VEXTRACT v16i16->v8i16 and v32i8->v16i8. Disable ↵Craig Topper2016-05-212-1/+9
| | | | | | AVX2 versions of vector extract when AVX512VL is enabled. llvm-svn: 270318
* [AVX512] Disable AVX2 VPERMD, VPERMQ, VPERMPS, and VPERMPD patterns when ↵Craig Topper2016-05-212-30/+38
| | | | | | AVX512VL is enabled. Also add shuffle comment printing for AVX512VL VPERMPD/VPERMQ to keep some tests that now use these instructions instead of the AVX2 ones. llvm-svn: 270317
* [AVX512] Disable AVX/AVX2 VBROADCASTSS/VBROADCASTSD patterns when AVX512VL ↵Craig Topper2016-05-211-4/+4
| | | | | | is enabled. llvm-svn: 270316
* [AVX512] Disable AVX/AVX2 patterns for VPSADBW and VPMULUDQ when the ↵Craig Topper2016-05-211-4/+4
| | | | | | AVX512VL/AVX512BWI equivalents are available. llvm-svn: 270311
* [X86] Convert some SSE2/AVX2 intrinsics to ISD opcodes during lowering ↵Craig Topper2016-05-212-12/+24
| | | | | | instead of pattern matching the intrinsics. This unifies handling with AVX512 and allows these intrinsics to select EVEX encoded instructions to increase available registers. llvm-svn: 270310
* Address post-review for r270246David Majnemer2016-05-201-11/+13
| | | | | | | | | This gets rid of some unnecessary SmallStrings in X86TargetMachine::getSubtargetImpl. No functionality change is intended. llvm-svn: 270270
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