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* X86: Prefer using VPSHUFD over VPERMIL because it has better throughput.Nadav Rotem2012-12-071-3/+4
| | | | llvm-svn: 169624
* Replace r169459 with something safer. Rather than having computeMaskedBits toEvan Cheng2012-12-062-38/+25
| | | | | | | | | | understand target implementation of any_extend / extload, just generate zero_extend in place of any_extend for liveouts when the target knows the zero_extend will be implicit (e.g. ARM ldrb / ldrh) or folded (e.g. x86 movz). rdar://12771555 llvm-svn: 169536
* Remove unneeded function, since PR8156 was fixed over a year ago.Jakub Staszak2012-12-061-18/+1
| | | | llvm-svn: 169534
* Simplify code.Jakub Staszak2012-12-061-3/+1
| | | | llvm-svn: 169521
* Remove intrinsic specific instructions for (V)MOVQUmr with patterns pointing ↵Craig Topper2012-12-061-13/+5
| | | | | | to the normal instructions. llvm-svn: 169482
* Mark MOVDQ(A/U)rm as ReMaterializable. Mark all MOVDQ(A/U) instructions as ↵Craig Topper2012-12-062-4/+9
| | | | | | neverHasSideEffects. llvm-svn: 169477
* Let targets provide hooks that compute known zero and ones for any_extendEvan Cheng2012-12-062-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and extload's. If they are implemented as zero-extend, or implicitly zero-extend, then this can enable more demanded bits optimizations. e.g. define void @foo(i16* %ptr, i32 %a) nounwind { entry: %tmp1 = icmp ult i32 %a, 100 br i1 %tmp1, label %bb1, label %bb2 bb1: %tmp2 = load i16* %ptr, align 2 br label %bb2 bb2: %tmp3 = phi i16 [ 0, %entry ], [ %tmp2, %bb1 ] %cmp = icmp ult i16 %tmp3, 24 br i1 %cmp, label %bb3, label %exit bb3: call void @bar() nounwind br label %exit exit: ret void } This compiles to the followings before: push {lr} mov r2, #0 cmp r1, #99 bhi LBB0_2 @ BB#1: @ %bb1 ldrh r2, [r0] LBB0_2: @ %bb2 uxth r0, r2 cmp r0, #23 bhi LBB0_4 @ BB#3: @ %bb3 bl _bar LBB0_4: @ %exit pop {lr} bx lr The uxth is not needed since ldrh implicitly zero-extend the high bits. With this change it's eliminated. rdar://12771555 llvm-svn: 169459
* Added a option to the disassembler to print immediates as hex.Kevin Enderby2012-12-051-4/+4
| | | | | | | | | | | | | | | | | | | | This is for the lldb team so most of but not all of the values are to be printed as hex with this option. Some small values like the scale in an X86 address were requested to printed in decimal without the leading 0x. There may be some tweaks need to places that may still be in decimal that they want in hex. Specially for arm. I made my best guess. Any tweaks from here should be simple. I also did the best I know now with help from the C++ gurus creating the cleanest formatImm() utility function and containing the changes. But if someone has a better idea to make something cleaner I'm all ears and game for changing the implementation. rdar://8109283 llvm-svn: 169393
* Simplified BLEND pattern matching for shuffles.Elena Demikhovsky2012-12-054-78/+68
| | | | | | Generate VPBLENDD for AVX2 and VPBLENDW for v16i16 type on AVX2. llvm-svn: 169366
* Add x86 isel lowering logic to form bit test with inverted condition. e.g.Evan Cheng2012-12-051-6/+17
| | | | | | | | | x ^ -1. Patch by David Majnemer. rdar://12755626 llvm-svn: 169339
* Make NaCl naming consistent. The triple OSType is called NaCl and is representedEli Bendersky2012-12-041-1/+1
| | | | | | | | | textually as NativeClient. Also added a link to the native client project for readers unfamiliar with it. A Clang patch will follow shortly. llvm-svn: 169291
* Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth2012-12-046-13/+13
| | | | | | | | | | missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-0321-95/+94
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* rdar://12100355 (part 1)Shuxin Yang2012-11-293-1/+20
| | | | | | | | | | | | | | This revision attempts to recognize following population-count pattern: while(a) { c++; ... ; a &= a - 1; ... }, where <c> and <a>could be used multiple times in the loop body. TODO: On X8664 and ARM, __buildin_ctpop() are not expanded to a efficent instruction sequence, which need to be improved in the following commits. Reviewed by Nadav, really appreciate! llvm-svn: 168931
* I changed hasAVX() to hasFp256() and hasAVX2() to hasInt256() in ↵Elena Demikhovsky2012-11-292-102/+104
| | | | | | | | X86IselLowering.cpp. The logic was not changed, only names. llvm-svn: 168875
* Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen2012-11-281-3/+3
| | | | | | This class has been merged into its super-class TargetInstrInfo. llvm-svn: 168760
* X86: do not fold load instructions such as [V]MOVS[S|D] to other instructionsManman Ren2012-11-271-0/+15
| | | | | | | | | | | when the destination register is wider than the memory load. These load instructions load from m32 or m64 and set the upper bits to zero, while the folded instructions may accept m128. rdar://12721174 llvm-svn: 168710
* Remove the X86 Maximal Stack Alignment Check pass as it is no longer necessary.Chad Rosier2012-11-263-50/+0
| | | | | | | | | | | | | | | This pass was conservative in that it always reserved the FP to enable dynamic stack realignment, which allowed the RA to use aligned spills for vector registers. This happens even when spills were not necessary. The RA has since been improved to use unaligned spills when necessary. The new behavior is to realign the stack if the frame pointer was already reserved for some other reason, but don't reserve the frame pointer just because a function contains vector virtual registers. Part of rdar://12719844 llvm-svn: 168627
* Normalize splat 256bit vectors with 8 elements.Jakub Staszak2012-11-261-1/+1
| | | | llvm-svn: 168600
* Decouple MCInstBuilder from the streamer per Eli's request.Benjamin Kramer2012-11-261-17/+14
| | | | llvm-svn: 168597
* Add MCInstBuilder, a utility class to simplify MCInst creation similar to ↵Benjamin Kramer2012-11-261-39/+22
| | | | | | | | MachineInstrBuilder. Simplify some repetitive code with it. No functionality change. llvm-svn: 168587
* Fix execution domain for packed FMA4 instructions.Craig Topper2012-11-212-28/+30
| | | | llvm-svn: 168417
* Mark ISD::FMA as Legal instead of custom for x86 with FMA3/FMA4. Needed so ↵Craig Topper2012-11-211-6/+6
| | | | | | that llvm.muladd can be converted to ISD::FMA for fp_contract. llvm-svn: 168413
* Make calcLiveInMask method static.Jakub Staszak2012-11-211-1/+1
| | | | llvm-svn: 168409
* Make isScratchReg and isFPCopy methods static.Jakub Staszak2012-11-211-2/+2
| | | | llvm-svn: 168407
* Add obvious constantness.Jakub Staszak2012-11-201-3/+3
| | | | llvm-svn: 168396
* Intel OCL built-ins calling conventions now support MacOS 32-bit.Elena Demikhovsky2012-11-201-23/+24
| | | | llvm-svn: 168359
* Add the Erlang/HiPE calling convention, patch by Yiannis Tsiouris.Duncan Sands2012-11-163-5/+63
| | | | llvm-svn: 168166
* Use roundps/pd for llvm.ceil, llvm.trunc, llvm.rint, and llvm.nearbyint of ↵Craig Topper2012-11-162-0/+68
| | | | | | vector types. llvm-svn: 168141
* Return 0 instead of false.Jakub Staszak2012-11-151-3/+3
| | | | llvm-svn: 168076
* Simplify code.Jakub Staszak2012-11-151-1/+1
| | | | llvm-svn: 168064
* Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics.Craig Topper2012-11-151-1/+5
| | | | llvm-svn: 168025
* Remove unneeded #includes.Jakub Staszak2012-11-141-3/+0
| | | | llvm-svn: 168006
* X86: Enable SSE memory intrinsics even when stack alignment is less than 16 ↵Benjamin Kramer2012-11-141-7/+2
| | | | | | | | | | | | | | | | | | bytes. The stack realignment code was fixed to work when there is stack realignment and a dynamic alloca is present so this shouldn't cause correctness issues anymore. Note that this also enables generation of AVX instructions for memset under the assumptions: - Unaligned loads/stores are always fast on CPUs supporting AVX - AVX is not slower than SSE We may need some tweaked heuristics if one of those assumptions turns out not to be true. Effectively reverts r58317. Part of PR2962. llvm-svn: 167967
* X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches.Jim Grosbach2012-11-142-9/+42
| | | | | | | | | | When an instruction as written requires 32-bit mode and we're assembling in 64-bit mode, or vice-versa, issue a more specific diagnostic about what's wrong. rdar://12700702 llvm-svn: 167937
* Factor out an overly replicated typecast. No functional change.Craig Topper2012-11-141-65/+66
| | | | llvm-svn: 167916
* Use TARGET2 relocation for TType references on ARM.Anton Korobeynikov2012-11-142-7/+7
| | | | | | | | Do some cleanup of the code while here. Inspired by patch by Logan Chien! llvm-svn: 167904
* X86: when constructing VZEXT_LOAD from other loads, makes sure its outputManman Ren2012-11-131-0/+12
| | | | | | | | | | | chain is correctly setup. As an example, if the original load must happen before later stores, we need to make sure the constructed VZEXT_LOAD is constrained to be before the stores. rdar://12684358 llvm-svn: 167859
* Fix PR14314Michael Liao2012-11-121-2/+2
| | | | | | | - Fix operand order for atomic sub, where the minuend is the value loaded from memory and the subtrahend is the parameter specified. llvm-svn: 167718
* Move some helper methods to being static functions in the implementation file.Craig Topper2012-11-112-20/+7
| | | | llvm-svn: 167696
* Remove unnecessary subtraction and addition by 1 around a couple for loops.Craig Topper2012-11-101-6/+6
| | | | llvm-svn: 167673
* Tidy up spacing. No functional change.Craig Topper2012-11-101-4/+4
| | | | llvm-svn: 167671
* Removed unimplemented method declaration.Craig Topper2012-11-101-1/+0
| | | | llvm-svn: 167670
* Simplify custom emitter code for pcmp(e/i)str(i/m) and make the helper ↵Craig Topper2012-11-102-96/+42
| | | | | | functions static. llvm-svn: 167669
* Cleanup pcmp(e/i)str(m/i) instruction definitions and load folding support.Craig Topper2012-11-104-161/+192
| | | | llvm-svn: 167652
* Switch FreeBSD/i386 back to 4byte stack alignment. This partiallyRoman Divacky2012-11-091-3/+3
| | | | | | reverts r126226. llvm-svn: 167632
* indentNadav Rotem2012-11-091-2/+2
| | | | llvm-svn: 167607
* Add support of RTM from TSX extensionMichael Liao2012-11-0811-46/+159
| | | | | | | | - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region llvm-svn: 167573
* Simplify code. No functionality change.Jakub Staszak2012-11-061-1/+1
| | | | llvm-svn: 167505
* Make the helper functions static. No functional change.Nadav Rotem2012-11-061-3/+5
| | | | llvm-svn: 167501
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