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* [X86] Split off PHMINPOSUW to their own schedule classSimon Pilgrim2018-04-2411-12/+14
| | | | | | This also fixes Jaguar's schedule which was treating it as the WriteVecIMul default. llvm-svn: 330756
* [XOP] v4i32 IFMA 'VPMACS' instructions should use the WritePMULLD schedule classSimon Pilgrim2018-04-241-15/+28
| | | | llvm-svn: 330751
* [AVX512] VPERMQ/VPERMPD/VPERMIL single op shuffles are not variable shufflesSimon Pilgrim2018-04-241-4/+5
| | | | | | These variants all take an immediate shuffle mask value and should be scheduled as such. llvm-svn: 330747
* [X86][F16C] Add WriteCvtF2FSt scheduling classSimon Pilgrim2018-04-2412-48/+46
| | | | | | Fixes the classification of VCVTPS2PHmr/VCVTPS2PHYmr which were tagged as WriteCvtF2FLd_WriteRMW (PR36887) llvm-svn: 330737
* [X86][BtVer2] Fix VCVTPS2PHmr/VCVTPS2PHYmr latenciesSimon Pilgrim2018-04-241-2/+2
| | | | | | These are stores, not loads, so don't need to account for load latency. llvm-svn: 330735
* [X86] Remove unnecessary FMA reg-mem InstRW scheduler overrides.Simon Pilgrim2018-04-244-15/+1
| | | | llvm-svn: 330720
* [X86] Add vector element insertion/extraction scheduler classesSimon Pilgrim2018-04-2413-244/+184
| | | | | | | | | | | | Split off pinsr/pextr and extractps instructions. (Mostly) fixes PR36887. Note: It might be worth adding a WriteFInsertLd class as well in the future. Differential Revision: https://reviews.llvm.org/D45929 llvm-svn: 330714
* [X86] Replace action Promote with Expand for operation ISD::SINT_TO_FPAlexander Ivchenko2018-04-241-1/+3
| | | | | | | | | | | | | | | | | | | | | | | Summary: If attribute "use-soft-float"="true" is set then X86ISelLowering.cpp sets 'Promote' action for ISD::SINT_TO_FP operation on type i32. But 'Promote' action is not proper in this case since lib function __floatsidf is available for casting from signed int to float type. Thus Expand action is more suitable here. The Expand action should be set for ISD::UINT_TO_FP for soft float as well. If function attribute "use-soft-float"="true" is set then infinite looping can happen in DAG combining, function visitSINT_TO_FP() replaces SINT_TO_FP node with UINT_TO_FP node and function combineUIntToFP() replace vice versa in cycle. The fix prevents it. Patch by vrybalov Differential Revision: https://reviews.llvm.org/D45572 llvm-svn: 330711
* Correct dwarf unwind information in function epiloguePetar Jovanovic2018-04-243-21/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
* [X86] Add a BSWAP16 instruction using the 32-bit encoding plus a 0x66 prefix.Craig Topper2018-04-241-2/+6
| | | | | | This encoding is recognized by the CPU, but the behavior is undefined. This makes the disassembler handle it correctly so we don't print bswapl with a 16-bit register. llvm-svn: 330682
* [X86] Remove unnecessary vector memory folded InstRW overrides.Simon Pilgrim2018-04-234-187/+4
| | | | | | We have test coverage for these with resources-sse*/avx* llvm-svn: 330662
* [X86] Remove unnecessary BMI2 InstRW overrides.Simon Pilgrim2018-04-233-30/+6
| | | | | | We have test coverage for these with resources-bmi2.s llvm-svn: 330659
* [X86] Remove unnecessary WriteLEA InstRW overrides.Simon Pilgrim2018-04-235-16/+5
| | | | llvm-svn: 330648
* [X86] Revert r330638 - accidental commitGabor Buella2018-04-236-58/+2
| | | | llvm-svn: 330640
* [X86] movdiri and movdir64b instructionsGabor Buella2018-04-236-2/+58
| | | | | Reviewers: craig.topper llvm-svn: 330638
* [X86] Replace x87 instregex with instrs if they only match one instructionSimon Pilgrim2018-04-236-43/+37
| | | | llvm-svn: 330611
* [X86] Remove instregex matching from CLAC/STAC.Simon Pilgrim2018-04-232-8/+4
| | | | | | Note - noticed this as the STAC case as it was unintentionally matching against *STACK* pseudo instructions. llvm-svn: 330588
* [X86] Remove unnecessary MMX reg-mem InstRW scheduler overrides.Simon Pilgrim2018-04-236-122/+9
| | | | llvm-svn: 330581
* [X86] Add VEX_WIG to VEX encoded version of VCMPPSY/VCMPPDY.Craig Topper2018-04-231-2/+2
| | | | llvm-svn: 330563
* [X86][Znver1] Remove unnecessary BMI1 ANDN InstRW overrides.Simon Pilgrim2018-04-221-6/+0
| | | | llvm-svn: 330558
* [X86] Remove unnecessary WriteFBlend/WriteBlend InstRW overrides.Simon Pilgrim2018-04-225-34/+12
| | | | | | Fixed a lot of the default classes which were being completely overridden. llvm-svn: 330554
* [X86] Remove unnecessary WriteFMul/WriteFRcp/WriteFRsqrt InstRW overrides.Simon Pilgrim2018-04-223-38/+8
| | | | llvm-svn: 330553
* [X86] Remove unnecessary CVT instrw overrides.Simon Pilgrim2018-04-223-13/+0
| | | | llvm-svn: 330552
* [X86][SkylakeServer] Remove unnecessary PMULLD instrw overrides.Simon Pilgrim2018-04-221-21/+0
| | | | llvm-svn: 330549
* [X86][Atom] Remove unnecessary scalar/vector load/move instrw overrides.Simon Pilgrim2018-04-221-6/+5
| | | | llvm-svn: 330548
* [X86] Fix (completely overridden) WriteFHAdd/WritePHAdd classes to allow us ↵Simon Pilgrim2018-04-225-159/+14
| | | | | | to remove unnecessary instrw overrides. llvm-svn: 330546
* [X86][MMX][SSE] Tag missed PHADD/PHSUB instructions with WritePHAdd Simon Pilgrim2018-04-222-5/+5
| | | | llvm-svn: 330545
* [X86] Remove unnecessary WriteFVarBlend/WriteVarBlend InstRW overrides.Simon Pilgrim2018-04-225-117/+17
| | | | | | This also fixes some of the ReadAfterLd issues due to InstRW. llvm-svn: 330544
* [X86] Fix WriteMPSAD/WritePSADBW values to allow us to remove unnecessary ↵Simon Pilgrim2018-04-225-71/+8
| | | | | | instrw overrides. llvm-svn: 330542
* [X86][SandyBridge] Remove unnecessary WritePOPCNTLd overrides by fixing load ↵Simon Pilgrim2018-04-221-2/+1
| | | | | | latency. llvm-svn: 330541
* [X86] Change TB to PS on LFENCE instruction.Craig Topper2018-04-221-1/+1
| | | | | | This matches the other FENCE instructions. llvm-svn: 330533
* [X86] Remove OpSizeIgnore, it's not implemented any differently than ↵Craig Topper2018-04-223-7/+3
| | | | | | OpSizeFixed. llvm-svn: 330532
* [X86] Remove DATA32_PREFIX. Hack the printing for DATA16_PREFIX to print ↵Craig Topper2018-04-224-12/+25
| | | | | | | | | | 'data32' in 16-bit mode. Hack the asm parser to convert 'data32' to 'data16' in 16-bit mode. Improve the error messages to match GNU assembler. This also allows us to remove the hack from the disassembler table building. llvm-svn: 330531
* [X86] Strip unnecessary prefetch + vector move/load instrw overrides from ↵Simon Pilgrim2018-04-215-143/+6
| | | | | | scheduler models. llvm-svn: 330527
* [X86] Strip unnecessary WriteCvtF2I instrw overrides from scheduler models.Simon Pilgrim2018-04-212-6/+2
| | | | llvm-svn: 330525
* [X86] Strip unnecessary broadcast/shuffle256 instrw overrides from scheduler ↵Simon Pilgrim2018-04-214-133/+5
| | | | | | models. llvm-svn: 330523
* [X86][AVX] VPERM2F128/VINSERTF128 should be a shuffle256 schedule like ↵Simon Pilgrim2018-04-212-4/+6
| | | | | | VPERM2I128/VINSERTI128 llvm-svn: 330522
* [X86] Strip unnecessary vector integer math, shift-imm, extend, shuffle, ↵Simon Pilgrim2018-04-214-398/+12
| | | | | | pack/unpack instruction instrw overrides from scheduler models. llvm-svn: 330521
* [X86] Add DAG combine to turn (trunc (srl (mul ext, ext), 16) into ↵Craig Topper2018-04-211-0/+57
| | | | | | | | PMULHW/PMULHUW. Ultimately I want to use this to remove the intrinsics for these instructions. llvm-svn: 330520
* [X86] Add SchedWrites for LDMXCSR/STMXCSR.Craig Topper2018-04-2111-58/+53
| | | | llvm-svn: 330517
* [X86][Haswell] Strip unnecessary WriteFAdd/WriteFHAdd instruction instrw ↵Simon Pilgrim2018-04-211-16/+2
| | | | | | overrides. llvm-svn: 330514
* [X86][Broadwell] Remove unnecessary VORPD/VORPS instrw override - missed in ↵Simon Pilgrim2018-04-211-2/+0
| | | | | | D45629 llvm-svn: 330513
* [X86] Strip unnecessary WriteFRcp/WriteFRsqrt instruction instrw overrides ↵Simon Pilgrim2018-04-214-42/+8
| | | | | | | | from scheduler models. The required the default skylake schedules to be updated - these were being completely overriden by the InstRW and the existing values not used at all. llvm-svn: 330510
* [X86] Strip unnecessary WriteFShuffle instruction instrw overrides from ↵Simon Pilgrim2018-04-214-143/+6
| | | | | | scheduler models. llvm-svn: 330508
* [X86][SandyBridge] Strip unnecessary MOVQ/CVT instruction instrw overrides.Simon Pilgrim2018-04-211-9/+3
| | | | llvm-svn: 330505
* [X86] Strip unnecessary MMX instruction instrw overrides from scheduler models.Simon Pilgrim2018-04-216-181/+9
| | | | llvm-svn: 330503
* [X86] Strip unnecessary x87 instruction instrw overrides from scheduler models.Simon Pilgrim2018-04-213-52/+4
| | | | llvm-svn: 330501
* [X86] Add WriteFSign/WriteFLogic scheduler classesSimon Pilgrim2018-04-2013-312/+59
| | | | | | | | | | | | | | Split the fp and integer vector logical instruction scheduler classes - older CPUs especially often handled these on different pipes. This unearthed a couple of things that are also handled in this patch: (1) We were tagging avx512 fp logic ops as WriteFAdd, probably because of the lack of WriteFLogic (2) SandyBridge had integer logic ops only using Port5, when afaict they can use Ports015. (3) Cleaned up x86 FCHS/FABS scheduling as they are typically treated as fp logic ops. Differential Revision: https://reviews.llvm.org/D45629 llvm-svn: 330480
* [X86][SandyBridge] Remove duplciate InstRWs from Sandy Brige scheduler model.Craig Topper2018-04-201-60/+6
| | | | llvm-svn: 330465
* [X86] WaitPKG instructionsGabor Buella2018-04-208-13/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Three new instructions: umonitor - Sets up a linear address range to be monitored by hardware and activates the monitor. The address range should be a writeback memory caching type. umwait - A hint that allows the processor to stop instruction execution and enter an implementation-dependent optimized state until occurrence of a class of events. tpause - Directs the processor to enter an implementation-dependent optimized state until the TSC reaches the value in EDX:EAX. Also modifying the description of the mfence instruction, as the rep prefix (0xF3) was allowed before, which would conflict with umonitor during disassembly. Before: $ echo 0xf3,0x0f,0xae,0xf0 | llvm-mc -disassemble .text mfence After: $ echo 0xf3,0x0f,0xae,0xf0 | llvm-mc -disassemble .text umonitor %rax Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45253 llvm-svn: 330462
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