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* Removed the "inline" keyword from the disassembler decoder,Sean Callanan2009-12-221-30/+30
| | | | | | because the Visual C++ build does not build .c files as C99 llvm-svn: 91935
* Fixes to the X86 disassembler:Sean Callanan2009-12-222-5/+17
| | | | | | | | Made LEA memory operands emit only 4 MCInst operands. Made the scale operand equal 1 for instructions that have no SIB byte. llvm-svn: 91919
* Remove target attribute break-sse-dep. Instead, do not fold load into sse ↵Evan Cheng2009-12-226-42/+18
| | | | | | partial update instructions unless optimizing for size. llvm-svn: 91910
* Include based on the current path, since we already -I the X86 target's ↵Douglas Gregor2009-12-221-1/+1
| | | | | | path. Fixes CMake build llvm-svn: 91908
* Add more plumbing. This time in the LowerArguments and "get" functions whichBill Wendling2009-12-221-1/+2
| | | | | | | | return partial registers. This affected the back-end lowering code some. Also patch up some places I missed before in the "get" functions. llvm-svn: 91880
* Changed REG_* to MODRM_REG_* to avoid conflictsSean Callanan2009-12-222-17/+21
| | | | | | with symbols in AuroraUX's global namespace. llvm-svn: 91879
* Fix some may-be-uninitialized var warnings.Daniel Dunbar2009-12-221-3/+3
| | | | llvm-svn: 91878
* Fixed library dependencies between the X86 disassembler andSean Callanan2009-12-223-18/+5
| | | | | | X86 codegen that were causing circular symbol dependencies. llvm-svn: 91871
* print pcrel immediates as signed values instead of unsigned so that weChris Lattner2009-12-221-3/+5
| | | | | | | | | | | | | | get things like this out of the disassembler: 0x100000ecb: callq -96 instead of: 0x100000ecb: callq 4294967200 rdar://7491123 llvm-svn: 91864
* Fix setting and default setting of code model for jit. Do thisEric Christopher2009-12-212-11/+25
| | | | | | | | | | by allowing backends to override routines that will default the JIT and Static code generation to an appropriate code model for the architecture. Should fix PR 5773. llvm-svn: 91824
* A couple minor README updates.Eli Friedman2009-12-211-14/+5
| | | | llvm-svn: 91823
* #if 0 out X86 disassembler for now, it is breaking the build in multiple places.Daniel Dunbar2009-12-192-0/+13
| | | | llvm-svn: 91778
* rename dprintf to dbgpritnf, in order to fix build with glibc (which already ↵Nuno Lopes2009-12-191-29/+29
| | | | | | defines dprintf in stdio.h llvm-svn: 91775
* Use memset instead of bzero, its more portable.Daniel Dunbar2009-12-191-2/+2
| | | | llvm-svn: 91754
* Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit Sean Callanan2009-12-199-5/+2823
| | | | | | | | | | | | | | | | | | | | incarnations), integrated into the MC framework. The disassembler is table-driven, using a custom TableGen backend to generate hierarchical tables optimized for fast decode. The disassembler consumes MemoryObjects and produces arrays of MCInsts, adhering to the abstract base class MCDisassembler (llvm/MC/MCDisassembler.h). The disassembler is documented in detail in - lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime) - utils/TableGen/DisassemblerEmitter.cpp (table emitter) You can test the disassembler by running llvm-mc -disassemble for i386 or x86_64 targets. Please let me know if you encounter any problems with it. llvm-svn: 91749
* Bump alignment requirements for windows targets to achieve compartibility ↵Anton Korobeynikov2009-12-191-0/+3
| | | | | | | | with vcpp. Based on patch by Michael Beck! llvm-svn: 91745
* On recent Intel u-arch's, folding loads into some unary SSE instructions canEvan Cheng2009-12-186-17/+82
| | | | | | | | | | | | | | | | | | | be non-optimal. To be precise, we should avoid folding loads if the instructions only update part of the destination register, and the non-updated part is not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks the partial register dependency and it can improve performance. e.g. movss (%rdi), %xmm0 cvtss2sd %xmm0, %xmm0 instead of cvtss2sd (%rdi), %xmm0 An alternative method to break dependency is to clear the register first. e.g. xorps %xmm0, %xmm0 cvtss2sd (%rdi), %xmm0 llvm-svn: 91672
* Re-apply 91623 now that I actually know what I was trying to do.Evan Cheng2009-12-181-25/+1
| | | | llvm-svn: 91655
* Instruction fixes, added instructions, and AsmString changes in theSean Callanan2009-12-189-423/+1236
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
* Revert r91623 to unbreak the buildbots.Jeffrey Yasskin2009-12-171-1/+4
| | | | llvm-svn: 91632
* Remove an unused option.Evan Cheng2009-12-171-4/+1
| | | | llvm-svn: 91623
* In LowerEXTRACT_VECTOR_ELT, force an i32 value type for PEXTWR instead ofKen Dyck2009-12-171-1/+1
| | | | | | | incrementing the simple value type of the 16-bit type, which would give the wrong type if an intemediate MVT (such as i24) were introduced. llvm-svn: 91602
* Re-enable 91381 with fixes.Evan Cheng2009-12-163-12/+40
| | | | llvm-svn: 91489
* Change indirect-globals to use a dedicated allocIndirectGV. This lets usJeffrey Yasskin2009-12-151-8/+10
| | | | | | | | | remove start/finishGVStub and the BufferState helper class from the MachineCodeEmitter interface. It has the side-effect of not setting the indirect global writable and then executable on ARM, but that shouldn't be necessary. llvm-svn: 91464
* Fix an encoding bug.Evan Cheng2009-12-151-1/+1
| | | | llvm-svn: 91417
* For fastcc on x86, let ECX be used as a return register after EAX and EDXKenneth Uildriks2009-12-151-1/+8
| | | | llvm-svn: 91410
* Disable 91381 for now. It's miscompiling ARMISelDAG2DAG.cpp.Evan Cheng2009-12-151-1/+3
| | | | llvm-svn: 91405
* Use sbb x, x to materialize carry bit in a GPR. The result is all one's or ↵Evan Cheng2009-12-154-3/+96
| | | | | | all zero's. llvm-svn: 91381
* Fix integer cast code to handle vector types.Dan Gohman2009-12-141-2/+11
| | | | llvm-svn: 91362
* Whitespace changes, comment clarification. No functional changes.Bill Wendling2009-12-141-15/+26
| | | | llvm-svn: 91274
* Disable r91104 for x86. It causes partial register stall which pessimize ↵Evan Cheng2009-12-121-12/+12
| | | | | | code in 32-bit. llvm-svn: 91223
* Add comment about potential partial register stall.Evan Cheng2009-12-121-0/+5
| | | | llvm-svn: 91220
* Fix an obvious bug. No test case since LEA16r is not being used.Evan Cheng2009-12-121-1/+1
| | | | llvm-svn: 91219
* Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.Dan Gohman2009-12-111-0/+1
| | | | llvm-svn: 91158
* Honour setHasCalls() set from isel.Anton Korobeynikov2009-12-111-0/+5
| | | | | | | This is used in some weird cases like general dynamic TLS model. This fixes PR5723 llvm-svn: 91144
* Add support to 3-addressify 16-bit instructions.Evan Cheng2009-12-112-88/+135
| | | | llvm-svn: 91104
* Optimize splat of a scalar load into a shuffle of a vector load when it's ↵Evan Cheng2009-12-093-4/+93
| | | | | | | | | | | | legal. e.g. vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0> => vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1> iff ptr is 16-byte aligned (or can be made into 16-byte aligned). llvm-svn: 90984
* Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 ↵Evan Cheng2009-12-091-11/+1
| | | | | | isl lowering code. llvm-svn: 90925
* Move isConsecutiveLoad to SelectionDAG. It's not target dependent and it's ↵Evan Cheng2009-12-091-1/+1
| | | | | | primary used by selectdag passes. llvm-svn: 90922
* Don't enable the post-RA scheduler on x86 except at -O3. In itsDan Gohman2009-12-071-1/+1
| | | | | | current form, it is too expensive in compile time. llvm-svn: 90781
* Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor ofDan Gohman2009-12-052-22/+0
| | | | | | | MachineBasicBlock::canFallThrough(), which is target-independent and more thorough. llvm-svn: 90634
* Remove an unneeded include.David Greene2009-12-041-1/+0
| | | | llvm-svn: 90625
* Have hasLoad/StoreFrom/ToStackSlot return the relevant MachineMemOperand.David Greene2009-12-042-9/+21
| | | | llvm-svn: 90608
* yay for case insensitive file systems (?)Chris Lattner2009-12-031-1/+1
| | | | llvm-svn: 90370
* improve portability to avoid conflicting with std::next in c++'0x.Chris Lattner2009-12-034-6/+7
| | | | | | Patch by Howard Hinnant! llvm-svn: 90365
* Factor the stack alignment calculations out into a target independent pass.Jim Grosbach2009-12-023-67/+2
| | | | | | No functionality change. llvm-svn: 90336
* Minor whitespace fixes.Dan Gohman2009-11-302-2/+1
| | | | llvm-svn: 90166
* Fix a minor inconsistency.Dan Gohman2009-11-301-1/+1
| | | | llvm-svn: 90165
* Remove isProfitableToDuplicateIndirectBranch target hook. It is profitableBob Wilson2009-11-301-2/+0
| | | | | | | | | for all the processors where I have tried it, and even when it might not help performance, the cost is quite low. The opportunities for duplicating indirect branches are limited by other factors so code size does not change much due to tail duplicating indirect branches aggressively. llvm-svn: 90144
* Added support to allow clients to custom widen. For X86, custom widen ↵Mon P Wang2009-11-301-0/+21
| | | | | | | | | vectors for divide/remainder since these operations can trap by unroll them and adding undefs for the resulting vector. llvm-svn: 90108
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