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* [ms-inline asm] Do not omit the frame pointer if we have ms-inline assembly.Chad Rosier2013-02-161-1/+1
| | | | | | | | | | | If the frame pointer is omitted, and any stack changes occur in the inline assembly, e.g.: "pusha", then any C local variable or C argument references will be incorrect. I pass no judgement on anyone who would do such a thing. ;) rdar://13218191 llvm-svn: 175334
* Temporary revert of 175320.Bill Wendling2013-02-152-42/+34
| | | | llvm-svn: 175322
* Reinitialize the ivars in the subtarget.Bill Wendling2013-02-152-34/+42
| | | | | | | When we're recalculating the feature set of the subtarget, we need to have the ivars in their initial state. llvm-svn: 175320
* Use the 'target-features' and 'target-cpu' attributes to reset the subtarget ↵Bill Wendling2013-02-152-41/+67
| | | | | | | | | | features. If two functions require different features (e.g., `-mno-sse' vs. `-msse') then we want to honor that, especially during LTO. We can do that by resetting the subtarget's features depending upon the 'target-feature' attribute. llvm-svn: 175314
* [ms-inline asm] Adjust the EndLoc to account for the ']'.Chad Rosier2013-02-151-1/+2
| | | | llvm-svn: 175312
* Give these callbacks hidden visibility. It is better to not export them moreRafael Espindola2013-02-151-1/+2
| | | | | | | than we need to and some ELF linkers complain about directly accessing symbols with default visibility. llvm-svn: 175268
* Don't make assumptions about the mangling of static functions in extern "C"Rafael Espindola2013-02-151-20/+10
| | | | | | | | blocks. We still don't have consensus if we should try to change clang or the standard, but llvm should work with compilers that implement the current standard and mangle those functions. llvm-svn: 175267
* Make helpers static. Add missing include so LLVMInitializeObjCARCOpts gets C ↵Benjamin Kramer2013-02-151-1/+1
| | | | | | linkage. llvm-svn: 175264
* The operand listing is very much outdated.Eli Bendersky2013-02-141-5/+2
| | | | llvm-svn: 175220
* Simplify code. Remove "else after return".Jakub Staszak2013-02-141-5/+4
| | | | llvm-svn: 175212
* added basic support for Intel ADX instructionsKay Tiong Khoo2013-02-145-0/+54
| | | | | | -feature flag, instructions definitions, test cases llvm-svn: 175196
* 80-colNadav Rotem2013-02-141-1/+2
| | | | llvm-svn: 175189
* Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).Elena Demikhovsky2013-02-141-3/+17
| | | | | | Added a test. llvm-svn: 175144
* Revert r175120 and r175121. Clang is producing the expected asm names again.Rafael Espindola2013-02-141-0/+6
| | | | llvm-svn: 175133
* Don't assume the mangling of static functions.Rafael Espindola2013-02-141-6/+0
| | | | llvm-svn: 175121
* Don't build tail calls to functions with three inreg arguments on x86-32 PIC.Nick Lewycky2013-02-131-5/+11
| | | | | | Fixes PR15250! llvm-svn: 175092
* [ms-inline-asm] Add support for memory references that have non-immediateChad Rosier2013-02-131-13/+18
| | | | | | | displacements. rdar://12974533 llvm-svn: 175083
* X86: Disable generation of rep;movsl when %esi is used as a base pointer.Benjamin Kramer2013-02-131-0/+8
| | | | | | | | | | | This happens when there is both stack realignment and a dynamic alloca in the function. If we overwrite %esi (rep;movsl uses fixed registers) we'll lose the base pointer and the next register spill will write into oblivion. Fixes PR15249 and unbreaks firefox on i386/freebsd. Mozilla uses dynamic allocas and freebsd a 4 byte stack alignment. llvm-svn: 175057
* Prevent insertion of "vzeroupper" before call that preserves YMM registers, ↵Elena Demikhovsky2013-02-131-0/+10
| | | | | | since a caller uses preserved registers across the call. llvm-svn: 175043
* Check i1 as well as i8 variables for 8 bit registers for x86 inlineEric Christopher2013-02-131-1/+1
| | | | | | assembly. llvm-svn: 175036
* Added 0x0D to 2-byte opcode extension table for prefetch* variantsKay Tiong Khoo2013-02-121-4/+2
| | | | | | | Fixed decode of existing 3dNow prefetchw instruction Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs llvm-svn: 174920
* *fixed disassembly of some i386 system insts with intel syntaxKay Tiong Khoo2013-02-111-4/+4
| | | | | | *added file for test cases for i386 intel syntax llvm-svn: 174900
* This is a follow-up on r174446, now taking Atom processors intoEli Bendersky2013-02-061-6/+6
| | | | | | | | | | | | account. Atoms use LEA for updating SP in prologs/epilogs, and the exact LEA opcode depends on the data model. Also reapplying the test case which was added and then reverted (because of Atom failures), this time specifying explicitly the CPU in addition to the triple. The test case now checks all variations (data mode, cpu Atom vs. Core). llvm-svn: 174542
* Make sure the correct opcodes are used to SUB and ADD the stackEli Bendersky2013-02-051-13/+18
| | | | | | | pointer in function prologs/epilogs. The opcodes should depend on the data model (LP64 vs. ILP32) rather than the architecture bit-ness. llvm-svn: 174446
* Move MRI liveouts to X86 return instructions.Jakob Stoklund Olesen2013-02-052-12/+12
| | | | llvm-svn: 174402
* Fix commentsEli Bendersky2013-02-051-1/+1
| | | | llvm-svn: 174390
* X86: Open up some opportunities for constant folding by postponing shift ↵Benjamin Kramer2013-02-041-4/+2
| | | | | | | | lowering. Fixes PR15141. llvm-svn: 174327
* X86: Simplify code. No functionality change.Benjamin Kramer2013-02-041-19/+5
| | | | llvm-svn: 174326
* More MSan/ASan annotations.Evgeniy Stepanov2013-02-041-0/+3
| | | | | | | | | | | | | | This change lets us bootstrap LLVM/Clang under ASan and MSan. It contains fixes for 2 issues: - X86JIT reads return address from stack, which MSan does not know is initialized. - bugpoint tests run binaries with RLIMIT_AS. This does not work with certain Sanitizers. We are no longer including config.h in Compiler.h with this change. llvm-svn: 174306
* Two changes relevant to LEA and x32:David Sehr2013-02-013-3/+17
| | | | | | | | | 1) allows the use of RIP-relative addressing in 32-bit LEA instructions under x86-64 (ILP32 and LP64) 2) separates the size of address registers in 64-bit LEA instructions from control by ILP32/LP64. llvm-svn: 174208
* [PEI] Pass the frame index operand number to the eliminateFrameIndex function.Chad Rosier2013-01-312-16/+12
| | | | | | | Each target implementation was needlessly recomputing the index. Part of rdar://13076458 llvm-svn: 174083
* Whitespace.Eric Christopher2013-01-311-9/+9
| | | | llvm-svn: 174009
* Check and allow floating point registers to select the size of theEric Christopher2013-01-311-2/+2
| | | | | | | register for inline asm. This conforms to how gcc allows for effective casting of inputs into gprs (fprs is already handled). llvm-svn: 174008
* Restrict sin/cos optimization to 64-bit only for now. 32-bit is a bit messy ↵Evan Cheng2013-01-302-10/+14
| | | | | | and less critical. llvm-svn: 173987
* Remove dead code.Evan Cheng2013-01-291-10/+0
| | | | llvm-svn: 173812
* Fix typo in X86BaseInfo.h that I introduced in r157818.Hans Wennborg2013-01-291-2/+2
| | | | llvm-svn: 173798
* Merge SSE and AVX shuffle instructions in the comment printer.Craig Topper2013-01-291-98/+14
| | | | llvm-svn: 173777
* Teach SDISel to combine fsin / fcos into a fsincos node if the followingEvan Cheng2013-01-294-15/+91
| | | | | | | | | | | | | | | | | | conditions are met: 1. They share the same operand and are in the same BB. 2. Both outputs are used. 3. The target has a native instruction that maps to ISD::FSINCOS node or the target provides a sincos library call. Implemented the generic optimization in sdisel and enabled it for Mac OSX. Also added an additional optimization for x86_64 Mac OSX by using an alternative entry point __sincos_stret which returns the two results in xmm0 / xmm1. rdar://13087969 PR13204 llvm-svn: 173755
* Fix 256-bit PALIGNR comment decoding to understand that it works on ↵Craig Topper2013-01-281-2/+11
| | | | | | independent 256-bit lanes. llvm-svn: 173674
* Add missing break in 256-bit palignr comment printing. No test case yet ↵Craig Topper2013-01-281-0/+1
| | | | | | because the comment itself is still wrong. llvm-svn: 173669
* Fix inconsistent usage of PALIGN and PALIGNR when referring to the same ↵Craig Topper2013-01-287-34/+35
| | | | | | instruction. llvm-svn: 173667
* X86: Decode PALIGN operands so I don't have to do it in my head.Benjamin Kramer2013-01-264-1/+36
| | | | llvm-svn: 173572
* X86: Do splat promotion later, so the optimizer can chew on it first.Benjamin Kramer2013-01-261-10/+10
| | | | | | | | | | | | This catches many cases where we can emit a more efficient shuffle for a specific mask or when the mask contains undefs. Once the splat is lowered to unpacks we can't do that anymore. There is a possibility of moving the promotion after pshufb matching, but I'm not sure if pshufb with a mask loaded from memory is faster than 3 shuffles, so I avoided that for now. llvm-svn: 173569
* In this patch, we teach X86_64TargetMachine that it has a ILP32Eli Bendersky2013-01-254-18/+39
| | | | | | | | | | | | | | | | | | | | | (defined by the x32 ABI) mode, in which case its pointers are 32-bits in size. This knowledge is also added to X86RegisterInfo that now returns the appropriate registers in getPointerRegClass. There are many outcomes to this change. In order to keep the patches separate and manageable, we start by focusing on some simple testable cases. The patch adds a test with passing a pointer to a function - focusing on the difference between the two data models for x86-64. Another test is added for handling of 'sret' arguments (and functionality is added in X86ISelLowering to make it work). A note on naming: the "x32 ABI" document refers to the AMD64 architecture (in LLVM it's distinguished by being is64Bits() in the x86 subtarget) with two variations: the LP64 (default) data model, and the ILP32 data model. This patch adds predicates to the subtarget which are consistent with this naming scheme. llvm-svn: 173503
* Moving Cost Tables up to share with other targetsRenato Golin2013-01-241-48/+11
| | | | llvm-svn: 173382
* Fix an issue of pseudo atomic instruction DAG scheduleMichael Liao2013-01-222-3/+8
| | | | | | | | | | - Add list of physical registers clobbered in pseudo atomic insts Physical registers are clobbered when pseudo atomic instructions are expanded. Add them in clobber list to prevent DAG scheduler to mis-schedule them after these insns are declared side-effect free. - Add test case from Michael Kuperstein <michael.m.kuperstein@intel.com> llvm-svn: 173200
* X86: Make sure we account for the FMA4 register immediate value, otherwise ↵Benjamin Kramer2013-01-221-1/+1
| | | | | | | | rip-rel relocations will be off by one byte. PR15040. llvm-svn: 173176
* Initial patch for x32 ABI support.Eli Bendersky2013-01-221-3/+11
| | | | | | | | Add the x32 environment kind to the triple, and separate the concept of pointer size and callee save stack slot size, since they're not equal on x32. llvm-svn: 173175
* Make APFloat constructor require explicit semantics.Tim Northover2013-01-221-18/+30
| | | | | | | | | Previously we tried to infer it from the bit width size, with an added IsIEEE argument for the PPC/IEEE 128-bit case, which had a default value. This default value allowed bugs to creep in, where it was inappropriate. llvm-svn: 173138
* Use <0 checks in place of ==-1 because it results in simpler code.Craig Topper2013-01-211-3/+3
| | | | llvm-svn: 173010
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