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* Add XOP feature flag.Jan Sjödin2011-12-023-2/+12
| | | | llvm-svn: 145682
* Reduce duplicate code in isHorizontalBinOp and add some asserts to protect ↵Craig Topper2011-12-021-32/+24
| | | | | | assumptions llvm-svn: 145681
* Add instruction selection support for horizontal add/sub of 256-bit floating ↵Craig Topper2011-12-021-2/+4
| | | | | | point vectors. Also add the test case for 256-bit integer vectors. llvm-svn: 145680
* Dummy commit to check commit access.Sanjoy Das2011-12-011-1/+1
| | | | llvm-svn: 145619
* For 64-bit the rest of the general regs are ok for the q constraint. MakeEric Christopher2011-12-011-1/+17
| | | | | | | | sure we can emit both the high and low versions of those registers. Fixes rdar://10392864 llvm-svn: 145579
* Pass AVX vectors which are arguments to varargs functions on the stack. ↵Eli Friedman2011-12-011-4/+9
| | | | | | <rdar://problem/10463281>. llvm-svn: 145573
* Support for encoding all FMA4 instructions and tablegen patterns for allJan Sjödin2011-11-301-0/+349
| | | | | | remaining FMA4 instructions and intrinsics with tests. llvm-svn: 145525
* X86: Turns out bulldozer also supports sse42 and lzcnt.Benjamin Kramer2011-11-301-11/+6
| | | | | | | While at it remove the barcelona/instanbul/shanghai subtargets, they're unsupported by GCC and look pretty broken. llvm-svn: 145494
* X86: Add subtargets for AMD's bulldozer.Benjamin Kramer2011-11-301-0/+6
| | | | llvm-svn: 145493
* X86: PerformOrCombine introduced a vselect node with a wrong order of ↵Nadav Rotem2011-11-301-1/+1
| | | | | | operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479). llvm-svn: 145488
* Add instruction selection support for AVX2 horizontal add/sub instructions.Craig Topper2011-11-301-24/+49
| | | | llvm-svn: 145487
* Merge VPERM2F128/VPERM2I128 ISD node types.Craig Topper2011-11-304-71/+50
| | | | llvm-svn: 145485
* Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node ↵Craig Topper2011-11-307-142/+135
| | | | | | type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128. llvm-svn: 145483
* Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it ↵Evan Cheng2011-11-291-0/+6
| | | | | | was generating poor code for some SSE builtins. llvm-svn: 145448
* Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.Jakob Stoklund Olesen2011-11-295-28/+15
| | | | | | | | | Like V_SET0, these instructions are expanded by ExpandPostRA to xorps / vxorps so they can participate in execution domain swizzling. This also makes the AVX variants redundant. llvm-svn: 145440
* build/CMake: Finish removal of add_llvm_library_dependencies.Daniel Dunbar2011-11-297-53/+0
| | | | llvm-svn: 145420
* MC/X86/COFF: Allow quotes in names when targeting MS/Windows,Michael J. Spencer2011-11-293-5/+23
| | | | | | | | | | as MC is the only assembler we support. This splits MS/Windows and GNU/Windows ASM infos into two seperate classes. While there is currently only one difference, full MS C++ ABI support will require many more. llvm-svn: 145409
* Fixed vsqrt.ss intrinsic usage - order of input operands was wrong.Elena Demikhovsky2011-11-291-1/+1
| | | | | | | Added a test. Thanks Bruno for reviewing the patch. llvm-svn: 145403
* Fix shuffle decoding for memory forms for (V)SHUFPS/D.Craig Topper2011-11-291-6/+12
| | | | llvm-svn: 145392
* Fix issues in shuffle decoding around VPERM* instructions. Fix shuffle ↵Craig Topper2011-11-295-30/+82
| | | | | | decoding for VSHUFPS/D for 256-bit types. Add pattern matching for memory forms of VPERMILPS/VPERMILPD. llvm-svn: 145390
* Fix VINSERTF128/VEXTRACTF128 to be marked as FP instructions. Allow ↵Craig Topper2011-11-292-5/+9
| | | | | | execution dependency fix pass to convert them to their integer equivalents when AVX2 is enabled. llvm-svn: 145376
* Correctly mark VPERM2F128 as being an FP instruction and add execution ↵Craig Topper2011-11-292-1/+3
| | | | | | domain fixing support to convert it to VPERM2I128 for AVX2. llvm-svn: 145370
* Add missing avx pattern.Evan Cheng2011-11-281-0/+3
| | | | llvm-svn: 145272
* Add X86 instruction selection for VPERM2I128 when AVX2 is enabled. Merge ↵Craig Topper2011-11-284-110/+117
| | | | | | VPERMILPS/VPERMILPD detection since they are pretty similar. llvm-svn: 145238
* Make isCommutedVSHUFP more like the way isCommutedSHUFP is handled.Craig Topper2011-11-281-35/+81
| | | | llvm-svn: 145218
* Merge detecting and handling for VSHUFPSY and VSHUFPDY since a lot of the ↵Craig Topper2011-11-271-92/+39
| | | | | | code was similar for both. llvm-svn: 145199
* Merge 128-bit and 256-bit X86ISD node types for VPERMILPS and VPERMILPD. ↵Craig Topper2011-11-264-39/+15
| | | | | | Simplify some shuffle lowering code since V1 can never be UNDEF due to canonalizing that occurs when shuffle nodes are created. llvm-svn: 145153
* Collapse X86ISD node types for PUNPCKH*, PUNPCKL*, UNPCKLP*, and UNPCKHP* to ↵Craig Topper2011-11-264-178/+116
| | | | | | not be type specific. Now we just have integer high and low and floating point high and low. Pattern matching will choose the correct instruction based on the vector type. llvm-svn: 145148
* This patch contains support for encoding FMA4 instructions andBruno Cardoso Lopes2011-11-254-7/+86
| | | | | | | | | tablegen patterns for scalar FMA4 operations and intrinsic. Also add tests for vfmaddsd. Patch by Jan Sjodin llvm-svn: 145133
* Remove 256-bit specific node types for UNPCKHPS/D and instead use the ↵Craig Topper2011-11-244-50/+24
| | | | | | 128-bit versions and let the operand type disinquish. Also fix the load form of the v8i32 patterns for these to realize that the load would be promoted to v4i64. llvm-svn: 145126
* Remove AVX2 specific X86ISD node types for PUNPCKH/L and instead just reuse ↵Craig Topper2011-11-244-81/+33
| | | | | | the 128-bit versions and let the vector type distinguish. llvm-svn: 145125
* X86: alias cqo to cqto.Benjamin Kramer2011-11-241-1/+2
| | | | llvm-svn: 145121
* X86: Use btq for bit tests if the immediate can't be encoded in 32 bits.Benjamin Kramer2011-11-231-1/+9
| | | | | | | | | | | | | | | | Before: movabsq $4294967296, %rax ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00] testq %rax, %rdi ## encoding: [0x48,0x85,0xf8] jne LBB0_2 ## encoding: [0x75,A] After: btq $32, %rdi ## encoding: [0x48,0x0f,0xba,0xe7,0x20] jb LBB0_2 ## encoding: [0x72,A] btq is usually slower than testq because it doesn't fuse with the jump, but here we're better off saving one register and a giant movabsq. llvm-svn: 145103
* I added several lines in X86 code generator that allow to choose Elena Demikhovsky2011-11-231-15/+46
| | | | | | | | VSHUFPS/VSHUFPD instructions while lowering VECTOR_SHUFFLE node. I check a commuted VSHUFP mask. The patch was reviewed by Bruno. llvm-svn: 145099
* Fix PR11422.Jakob Stoklund Olesen2011-11-231-1/+4
| | | | | | | | | | | | | This was a bug in keeping track of the available domains when merging domain values. The wrong domain mask caused ExecutionDepsFix to try to move VANDPSYrr to the integer domain which is only available in AVX2. Also add an assertion to catch future attempts at emitting AVX2 instructions. llvm-svn: 145096
* More fixes to the X86InstComments for shuffle instructions. In particular ↵Craig Topper2011-11-223-44/+60
| | | | | | add AVX flavors of many instructions and fix the destination operand for some of the existing AVX entries. llvm-svn: 145063
* Fix shuffle decoding logic to handle UNPCKLPS/UNPCKLPD on 256-bit vectors ↵Craig Topper2011-11-224-21/+73
| | | | | | correctly. Add support for decoding UNPCKHPS/UNPCKHPD for AVX 128-bit and 256-bit forms. llvm-svn: 145055
* Add methods for querying minimum SSE version along with AVX. Simplifies all ↵Craig Topper2011-11-222-43/+38
| | | | | | the places that had to check a version of SSE and AVX. llvm-svn: 145053
* Lowering for v32i8 to VPUNPCKLBW/VPUNPCKHBW when AVX2 is enabled.Craig Topper2011-11-214-84/+30
| | | | llvm-svn: 145028
* Add support for lowering 256-bit shuffles to VPUNPCKL/H for i16, i32, i64 if ↵Craig Topper2011-11-214-47/+115
| | | | | | AVX2 is enabled. llvm-svn: 145026
* Make LowerSIGN_EXTEND_INREG split 256-bit vectors when AVX1 is enabled and ↵Craig Topper2011-11-211-8/+42
| | | | | | use AVX2 shifts when AVX2 is enabled. llvm-svn: 145022
* Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift ↵Craig Topper2011-11-202-45/+45
| | | | | | instructions. Remove 256-bit splat handling from LowerShift as it was already handled by PerformShiftCombine. llvm-svn: 145005
* Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled.Craig Topper2011-11-194-16/+33
| | | | llvm-svn: 145004
* Remove some of the special classes that worked around an old tablegen ↵Craig Topper2011-11-191-100/+50
| | | | | | limitation of not being able to remove redundant bitconverts from patterns. llvm-svn: 145003
* Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove ↵Craig Topper2011-11-192-74/+42
| | | | | | the intrinsic patterns. llvm-svn: 144999
* Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from ↵Craig Topper2011-11-194-3/+62
| | | | | | add/sub of appropriate shuffle vectors. llvm-svn: 144989
* Collapse X86 PSIGNB/PSIGNW/PSIGND node types.Craig Topper2011-11-194-33/+18
| | | | llvm-svn: 144988
* Extend VPBLENDVB and VPSIGN lowering to work for AVX2.Craig Topper2011-11-193-111/+127
| | | | llvm-svn: 144987
* Remove unused parameters from the AVX maskmov classes.Craig Topper2011-11-191-12/+6
| | | | llvm-svn: 144985
* Add AVX2 vpbroadcast supportNadav Rotem2011-11-182-28/+62
| | | | llvm-svn: 144967
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