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* Sorry about the churn. One more change to getOptimalMemOpType() hook. Did IEvan Cheng2012-12-122-14/+12
| | | | | | | | | | | | mention the inline memcpy / memset expansion code is a mess? This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset. The first indicates whether it is expanding a memset or a memcpy / memmove. The later is whether the memset is a memset of zero. It's totally possible (likely even) that targets may want to do different things for memcpy and memset of zero. llvm-svn: 169959
* - Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.Evan Cheng2012-12-122-11/+12
| | | | | | | | | Also added more comments to explain why it is generally ok to return true. - Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to be true for loaded source (memcpy) or zero constants (memset). The poor name choice is probably some kind of legacy issue. llvm-svn: 169954
* Avoid using lossy load / stores for memcpy / memset expansion. e.g.Evan Cheng2012-12-122-0/+15
| | | | | | f64 load / store on non-SSE2 x86 targets. llvm-svn: 169944
* Revert EVT->MVT changes, r169836-169851, due to buildbot failures.Patrik Hagglund2012-12-113-10/+10
| | | | llvm-svn: 169854
* Change TargetLowering::getTypeForExtArgOrReturn to take and returnPatrik Hagglund2012-12-112-5/+5
| | | | | | | | MVTs, instead of EVTs. Accordingly, add bitsLT (and similar) to MVT. llvm-svn: 169850
* Change TargetLowering::RegisterTypeForVT to contain MVTs, instead ofPatrik Hagglund2012-12-111-2/+2
| | | | | | EVTs. llvm-svn: 169848
* Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund2012-12-112-3/+3
| | | | | | of EVT. llvm-svn: 169845
* Fall back to the selection dag isel to select tail calls.Chad Rosier2012-12-111-0/+4
| | | | | | | | | | | | | | | | | | | This shouldn't affect codegen for -O0 compiles as tail call markers are not emitted in unoptimized compiles. Testing with the external/internal nightly test suite reveals no change in compile time performance. Testing with -O1, -O2 and -O3 with fast-isel enabled did not cause any compile-time or execution-time failures. All tests were performed on my x86 machine. I'll monitor our arm testers to ensure no regressions occur there. In an upcoming clang patch I will be marking the objc_autoreleaseReturnValue and objc_retainAutoreleaseReturnValue as tail calls unconditionally. While it's theoretically true that this is just an optimization, it's an optimization that we very much want to happen even at -O0, or else ARC applications become substantially harder to debug. Part of rdar://12553082 llvm-svn: 169796
* Some enhancements for memcpy / memset inline expansion.Evan Cheng2012-12-102-4/+10
| | | | | | | | | | | | | | | | | | | | | 1. Teach it to use overlapping unaligned load / store to copy / set the trailing bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies. 2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g. x86 and ARM. 3. When memcpy from a constant string, do *not* replace the load with a constant if it's not possible to materialize an integer immediate with a single instruction (required a new target hook: TLI.isIntImmLegal()). 4. Use unaligned load / stores more aggressively if target hooks indicates they are "fast". 5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8. Also increase the threshold to something reasonable (8 for memset, 4 pairs for memcpy). This significantly improves Dhrystone, up to 50% on ARM iOS devices. rdar://12760078 llvm-svn: 169791
* Revert "Make '-mtune=x86_64' assume fast unaligned memory accesses."Chandler Carruth2012-12-101-2/+1
| | | | | | Accidental commit... git svn betrayed me. Sorry for the noise. llvm-svn: 169741
* Make '-mtune=x86_64' assume fast unaligned memory accesses.Chandler Carruth2012-12-101-1/+2
| | | | | | | | | | | | | | | | | | | Summary: Not all chips targeted by x86_64 have this feature, but a dramatically increasing number do. Specifying a chip-specific tuning parameter will continue to turn the feature on or off as appropriate for that particular chip, but the generic flag should try to achieve the best performance on the most widely available hardware. Today, the number of chips with fast UA access dwarfs those without in the x86-64 space. Note that this also brings LLVM's code generation for this '-march' flag more in line with that of modern GCCs. CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D195 llvm-svn: 169740
* Fix a typo in my previous commit -- bloomfield is 0x1A not 0x2A.Chandler Carruth2012-12-101-1/+1
| | | | | | | Thanks to the PaX folks for noticing in review! We need some tests here, any sugestions welcome... llvm-svn: 169739
* Address a FIXME and update the fast unaligned memory feature for newerChandler Carruth2012-12-102-13/+21
| | | | | | | | | | | | | | | Intel chips. The model number rules were determined by inspecting Intel's documentation for their newer chip model numbers. My understanding is that all of the newer Intel chips have fast unaligned memory access, but if anyone is concerned about a particular chip, just shout. No tests updated; it's not clear we have dedicated tests for the chips' various features, but if anyone would like tests (or can point me at some existing ones), I'm happy to oblige. llvm-svn: 169730
* - Re-enable population count loop idiom recognization Shuxin Yang2012-12-093-1/+20
| | | | | | | - fix a bug which cause sigfault. - add two testing cases which was causing crash llvm-svn: 169687
* Revert the patches adding a popcount loop idiom recognition pass.Chandler Carruth2012-12-083-20/+1
| | | | | | | | | | | | | | There are still bugs in this pass, as well as other issues that are being worked on, but the bugs are crashers that occur pretty easily in the wild. Test cases have been sent to the original commit's review thread. This reverts the commits: r169671: Fix a logic error. r169604: Move the popcnt tests to an X86 subdirectory. r168931: Initial commit adding the pass. llvm-svn: 169683
* s/AttrListPtr/AttributeSet/g to better label what this class is going to be ↵Bill Wendling2012-12-071-1/+1
| | | | | | in the near future. llvm-svn: 169651
* When we use the BLEND instruction that uses the MSB as a mask, we can removeNadav Rotem2012-12-071-1/+6
| | | | | | | | the VSRI instruction before it since it does not affect the MSB. Thanks Craig Topper for suggesting this. llvm-svn: 169638
* X86: Prefer using VPSHUFD over VPERMIL because it has better throughput.Nadav Rotem2012-12-071-3/+4
| | | | llvm-svn: 169624
* Replace r169459 with something safer. Rather than having computeMaskedBits toEvan Cheng2012-12-062-38/+25
| | | | | | | | | | understand target implementation of any_extend / extload, just generate zero_extend in place of any_extend for liveouts when the target knows the zero_extend will be implicit (e.g. ARM ldrb / ldrh) or folded (e.g. x86 movz). rdar://12771555 llvm-svn: 169536
* Remove unneeded function, since PR8156 was fixed over a year ago.Jakub Staszak2012-12-061-18/+1
| | | | llvm-svn: 169534
* Simplify code.Jakub Staszak2012-12-061-3/+1
| | | | llvm-svn: 169521
* Remove intrinsic specific instructions for (V)MOVQUmr with patterns pointing ↵Craig Topper2012-12-061-13/+5
| | | | | | to the normal instructions. llvm-svn: 169482
* Mark MOVDQ(A/U)rm as ReMaterializable. Mark all MOVDQ(A/U) instructions as ↵Craig Topper2012-12-062-4/+9
| | | | | | neverHasSideEffects. llvm-svn: 169477
* Let targets provide hooks that compute known zero and ones for any_extendEvan Cheng2012-12-062-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and extload's. If they are implemented as zero-extend, or implicitly zero-extend, then this can enable more demanded bits optimizations. e.g. define void @foo(i16* %ptr, i32 %a) nounwind { entry: %tmp1 = icmp ult i32 %a, 100 br i1 %tmp1, label %bb1, label %bb2 bb1: %tmp2 = load i16* %ptr, align 2 br label %bb2 bb2: %tmp3 = phi i16 [ 0, %entry ], [ %tmp2, %bb1 ] %cmp = icmp ult i16 %tmp3, 24 br i1 %cmp, label %bb3, label %exit bb3: call void @bar() nounwind br label %exit exit: ret void } This compiles to the followings before: push {lr} mov r2, #0 cmp r1, #99 bhi LBB0_2 @ BB#1: @ %bb1 ldrh r2, [r0] LBB0_2: @ %bb2 uxth r0, r2 cmp r0, #23 bhi LBB0_4 @ BB#3: @ %bb3 bl _bar LBB0_4: @ %exit pop {lr} bx lr The uxth is not needed since ldrh implicitly zero-extend the high bits. With this change it's eliminated. rdar://12771555 llvm-svn: 169459
* Added a option to the disassembler to print immediates as hex.Kevin Enderby2012-12-051-4/+4
| | | | | | | | | | | | | | | | | | | | This is for the lldb team so most of but not all of the values are to be printed as hex with this option. Some small values like the scale in an X86 address were requested to printed in decimal without the leading 0x. There may be some tweaks need to places that may still be in decimal that they want in hex. Specially for arm. I made my best guess. Any tweaks from here should be simple. I also did the best I know now with help from the C++ gurus creating the cleanest formatImm() utility function and containing the changes. But if someone has a better idea to make something cleaner I'm all ears and game for changing the implementation. rdar://8109283 llvm-svn: 169393
* Simplified BLEND pattern matching for shuffles.Elena Demikhovsky2012-12-054-78/+68
| | | | | | Generate VPBLENDD for AVX2 and VPBLENDW for v16i16 type on AVX2. llvm-svn: 169366
* Add x86 isel lowering logic to form bit test with inverted condition. e.g.Evan Cheng2012-12-051-6/+17
| | | | | | | | | x ^ -1. Patch by David Majnemer. rdar://12755626 llvm-svn: 169339
* Make NaCl naming consistent. The triple OSType is called NaCl and is representedEli Bendersky2012-12-041-1/+1
| | | | | | | | | textually as NativeClient. Also added a link to the native client project for readers unfamiliar with it. A Clang patch will follow shortly. llvm-svn: 169291
* Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth2012-12-046-13/+13
| | | | | | | | | | missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-0321-95/+94
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* rdar://12100355 (part 1)Shuxin Yang2012-11-293-1/+20
| | | | | | | | | | | | | | This revision attempts to recognize following population-count pattern: while(a) { c++; ... ; a &= a - 1; ... }, where <c> and <a>could be used multiple times in the loop body. TODO: On X8664 and ARM, __buildin_ctpop() are not expanded to a efficent instruction sequence, which need to be improved in the following commits. Reviewed by Nadav, really appreciate! llvm-svn: 168931
* I changed hasAVX() to hasFp256() and hasAVX2() to hasInt256() in ↵Elena Demikhovsky2012-11-292-102/+104
| | | | | | | | X86IselLowering.cpp. The logic was not changed, only names. llvm-svn: 168875
* Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen2012-11-281-3/+3
| | | | | | This class has been merged into its super-class TargetInstrInfo. llvm-svn: 168760
* X86: do not fold load instructions such as [V]MOVS[S|D] to other instructionsManman Ren2012-11-271-0/+15
| | | | | | | | | | | when the destination register is wider than the memory load. These load instructions load from m32 or m64 and set the upper bits to zero, while the folded instructions may accept m128. rdar://12721174 llvm-svn: 168710
* Remove the X86 Maximal Stack Alignment Check pass as it is no longer necessary.Chad Rosier2012-11-263-50/+0
| | | | | | | | | | | | | | | This pass was conservative in that it always reserved the FP to enable dynamic stack realignment, which allowed the RA to use aligned spills for vector registers. This happens even when spills were not necessary. The RA has since been improved to use unaligned spills when necessary. The new behavior is to realign the stack if the frame pointer was already reserved for some other reason, but don't reserve the frame pointer just because a function contains vector virtual registers. Part of rdar://12719844 llvm-svn: 168627
* Normalize splat 256bit vectors with 8 elements.Jakub Staszak2012-11-261-1/+1
| | | | llvm-svn: 168600
* Decouple MCInstBuilder from the streamer per Eli's request.Benjamin Kramer2012-11-261-17/+14
| | | | llvm-svn: 168597
* Add MCInstBuilder, a utility class to simplify MCInst creation similar to ↵Benjamin Kramer2012-11-261-39/+22
| | | | | | | | MachineInstrBuilder. Simplify some repetitive code with it. No functionality change. llvm-svn: 168587
* Fix execution domain for packed FMA4 instructions.Craig Topper2012-11-212-28/+30
| | | | llvm-svn: 168417
* Mark ISD::FMA as Legal instead of custom for x86 with FMA3/FMA4. Needed so ↵Craig Topper2012-11-211-6/+6
| | | | | | that llvm.muladd can be converted to ISD::FMA for fp_contract. llvm-svn: 168413
* Make calcLiveInMask method static.Jakub Staszak2012-11-211-1/+1
| | | | llvm-svn: 168409
* Make isScratchReg and isFPCopy methods static.Jakub Staszak2012-11-211-2/+2
| | | | llvm-svn: 168407
* Add obvious constantness.Jakub Staszak2012-11-201-3/+3
| | | | llvm-svn: 168396
* Intel OCL built-ins calling conventions now support MacOS 32-bit.Elena Demikhovsky2012-11-201-23/+24
| | | | llvm-svn: 168359
* Add the Erlang/HiPE calling convention, patch by Yiannis Tsiouris.Duncan Sands2012-11-163-5/+63
| | | | llvm-svn: 168166
* Use roundps/pd for llvm.ceil, llvm.trunc, llvm.rint, and llvm.nearbyint of ↵Craig Topper2012-11-162-0/+68
| | | | | | vector types. llvm-svn: 168141
* Return 0 instead of false.Jakub Staszak2012-11-151-3/+3
| | | | llvm-svn: 168076
* Simplify code.Jakub Staszak2012-11-151-1/+1
| | | | llvm-svn: 168064
* Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics.Craig Topper2012-11-151-1/+5
| | | | llvm-svn: 168025
* Remove unneeded #includes.Jakub Staszak2012-11-141-3/+0
| | | | llvm-svn: 168006
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