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* Support for generating ELF objects on Windows.Andrew Kaylor2012-10-023-8/+15
| | | | | | This adds 'elf' as a recognized target triple environment value and overrides the default generated object format on Windows platforms if that value is present. This patch also enables MCJIT tests on Windows using the new environment value. llvm-svn: 165030
* [ms-inline asm] Add the convertToMapAndConstraints() function that is used toChad Rosier2012-10-011-29/+35
| | | | | | | | | | | map constraints and MCInst operands to inline asm operands. This replaces the getMCInstOperandNum() function. The logic to determine the constraints are not in place, so we still default to a register constraint (i.e., "r"). Also, we no longer build the MCInst but rather return just the opcode to get the MCInstrDesc. llvm-svn: 164979
* Use constants for all return values in switch. Allows clang to optimize it ↵Craig Topper2012-10-011-3/+8
| | | | | | into a lookup table. llvm-svn: 164926
* Change getX86SubSuperRegister to take an MVT::SimpleValueType rather than an ↵Craig Topper2012-09-304-11/+12
| | | | | | EVT and add llvm_unreachable to the switches. Helps it compile to dramatically better code. llvm-svn: 164919
* X86: when replacing SUB with TEST in ISelDAGToDAG, only replace uses of theManman Ren2012-09-281-5/+28
| | | | | | | | second output of SUB with first output of TEST. PR13966 llvm-svn: 164835
* Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. ↵Sylvestre Ledru2012-09-273-3/+3
| | | | | | See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 llvm-svn: 164768
* Fix a typo 'iff' => 'if'Sylvestre Ledru2012-09-273-3/+3
| | | | llvm-svn: 164767
* Remove the `hasFnAttr' method from Function.Bill Wendling2012-09-265-11/+11
| | | | | | | The hasFnAttr method has been replaced by querying the Attributes explicitly. No intended functionality change. llvm-svn: 164725
* X86_32: Large Symbol+Offset relocations.Jim Grosbach2012-09-261-8/+40
| | | | | | | | | | If the offset is more than 24-bits, it won't fit in a scattered relocation offset field, so we fall back to using a non-scattered relocation. rdar://12358909 llvm-svn: 164724
* Add SARX/SHRX/SHLX code generation supportMichael Liao2012-09-262-0/+61
| | | | llvm-svn: 164675
* Add RORX code generation supportMichael Liao2012-09-262-0/+27
| | | | llvm-svn: 164674
* Add MULX code generation supportMichael Liao2012-09-262-27/+83
| | | | llvm-svn: 164673
* Remove hasNoAVX method. Can just invert hasAVX instead.Craig Topper2012-09-262-7/+6
| | | | llvm-svn: 164664
* Add 'lock' prefix output support in assembly printerMichael Liao2012-09-263-33/+38
| | | | | | | | - Instead of embedding 'lock' into each mnemonic of atomic instructions except 'xchg', we teach X86 assembly printer to output 'lock' prefix similar to or consistent with code emitter. llvm-svn: 164659
* Add missing i64 max/min/umax/umin on 32-bit targetMichael Liao2012-09-253-0/+90
| | | | | | - Turn on atomic6432.ll and add specific test case as well llvm-svn: 164616
* Consistently specify the assembly variant to MatchInstructionImpl.Bob Wilson2012-09-251-4/+8
| | | | llvm-svn: 164611
* Fix an illegal tailcall opt where the callee returns a double via xmm while ↵Evan Cheng2012-09-252-1/+10
| | | | | | caller returns x86_fp80 via st0. rdar://12229511 llvm-svn: 164588
* Mark jump tables in code sections with DataRegion directives.Jim Grosbach2012-09-241-0/+5
| | | | | | | | | Even out-of-line jump tables can be in the code section, so mark them as data-regions for those targets which support the directives. rdar://12362871&12362974 llvm-svn: 164571
* Rather then have a wrapper function, have tblgen instantiate the implementation.Chad Rosier2012-09-241-7/+0
| | | | | | Also remove an unused argument. llvm-svn: 164567
* Rather then have a wrapper function, have tblgen instantiate the implementation.Chad Rosier2012-09-241-4/+0
| | | | llvm-svn: 164548
* Fix 16-bit atomic inst encoding and keep pseudo-inst starting with '#'Michael Liao2012-09-221-14/+14
| | | | llvm-svn: 164453
* Fix typo in r164357Michael Liao2012-09-221-1/+1
| | | | llvm-svn: 164452
* [ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.Chad Rosier2012-09-211-0/+4
| | | | llvm-svn: 164420
* Add comment.Chad Rosier2012-09-211-1/+2
| | | | llvm-svn: 164415
* Fix a typo in r164357Michael Liao2012-09-211-8/+8
| | | | llvm-svn: 164372
* Add missing i8 max/min/umax/umin supportMichael Liao2012-09-211-9/+44
| | | | | | - Fix PR5145 and turn on test 8-bit atomic ops llvm-svn: 164358
* Revise td of X86 atomic instructionsMichael Liao2012-09-213-218/+209
| | | | | | | - Rewirte most atomic instructions in templates for both better maintenance and future extensions, such as HLE in TSX. llvm-svn: 164357
* Re-work X86 code generation of atomic ops with spin-loopMichael Liao2012-09-205-540/+508
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Rewrite/merge pseudo-atomic instruction emitters to address the following issue: * Reduce one unnecessary load in spin-loop previously the spin-loop looks like thisMBB: newMBB: ld t1 = [bitinstr.addr] op t2 = t1, [bitinstr.val] not t3 = t2 (if Invert) mov EAX = t1 lcs dest = [bitinstr.addr], t3 [EAX is implicit] bz newMBB fallthrough -->nextMBB the 'ld' at the beginning of newMBB should be lift out of the loop as lcs (or CMPXCHG on x86) will load the current memory value into EAX. This loop is refined as: thisMBB: EAX = LOAD [MI.addr] mainMBB: t1 = OP [MI.val], EAX LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined] JNE mainMBB sinkMBB: * Remove immopc as, so far, all pseudo-atomic instructions has all-register form only, there is no immedidate operand. * Remove unnecessary attributes/modifiers in pseudo-atomic instruction td * Fix issues in PR13458 - Add comprehensive tests on atomic ops on various data types. NOTE: Some of them are turned off due to missing functionality. - Revise tests due to the new spin-loop generated. llvm-svn: 164281
* Unify the logic in SelectAtomicLoadAdd and SelectAtomicLoadArithMichael Liao2012-09-191-176/+140
| | | | | | | | | | | - Merge the processing of LOAD_ADD with other atomic load-arith operations - Separate the logic getting target constant for atomic-load-op and add an optimization for atomic-load-add on i16 with negative value - Optimize a minor case for atomic-fetch-add i16 with negative operand. Test case is revised. llvm-svn: 164243
* Remove code for setting the VEX L-bit as a function of operand size from the ↵Craig Topper2012-09-193-22/+2
| | | | | | code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. llvm-svn: 164204
* Add explicit VEX_L tags to all 256-bit instructions. This will allow us to ↵Craig Topper2012-09-193-240/+254
| | | | | | remove code from the code emitters that examined operands to set the L-bit. llvm-svn: 164202
* When creating MCAsmBackend pass the CPU string as well. In X86AsmBackendRoman Divacky2012-09-182-26/+34
| | | | | | | | | store this and use it to not emit long nops when the CPU is geode which doesnt support them. Fixes PR11212. llvm-svn: 164132
* Add some cases to x86 OptimizeCompare to handle DEC and INC, too.Jan Wen Voung2012-09-171-4/+14
| | | | | | While we are setting the earlier def to true, also make it live. llvm-svn: 164056
* LLVM_ATTRIBUTE_USED forces emission of a function. To silence unused ↵Benjamin Kramer2012-09-171-2/+2
| | | | | | function warnings use LLVM_ATTRIBUTE_UNUSED. llvm-svn: 164036
* The PMOVZXWD family of functions had patterns extends narrow vector types to ↵Nadav Rotem2012-09-161-0/+24
| | | | | | | | | | | wide vector types. It had patterns for zext-loading and extending. This commit adds patterns for loading a wide type, performing a bitcast, and extending. This is an odd pattern, but it is commonly used when writing code with intrinsics. rdar://11897677 llvm-svn: 163995
* Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.Craig Topper2012-09-151-2/+2
| | | | llvm-svn: 163974
* X86: Emitting x87 fsin/fcos for sinf/cosf is not safe without unsafe fp math.Benjamin Kramer2012-09-151-0/+2
| | | | | | This was only an issue if sse is disabled. llvm-svn: 163967
* Fix Doxygen issues:Dmitri Gribenko2012-09-141-2/+2
| | | | | | | | | | * wrap code blocks in \code ... \endcode; * refer to parameter names in paragraphs correctly (\arg is not what most people want -- it starts a new paragraph); * use \param instead of \arg to document parameters in order to be consistent with the rest of the codebase. llvm-svn: 163902
* Fix commentMichael Liao2012-09-131-1/+1
| | | | llvm-svn: 163835
* Add wider vector/integer support for PR12312Michael Liao2012-09-132-100/+103
| | | | | | | | - Enhance the fix to PR12312 to support wider integer, such as 256-bit integer. If more than 1 fully evaluated vectors are found, POR them first followed by the final PTEST. llvm-svn: 163832
* Fix the TCRETURNmi64 bug differently.Jakob Stoklund Olesen2012-09-131-2/+21
| | | | | | | | | | Add a PatFrag to match X86tcret using 6 fixed registers or less. This avoids folding loads into TCRETURNmi64 using 7 or more volatile registers. <rdar://problem/12282281> llvm-svn: 163819
* Revert r163761 "Don't fold indexed loads into TCRETURNmi64."Jakob Stoklund Olesen2012-09-133-39/+1
| | | | | | The patch caused "Wrong topological sorting" assertions. llvm-svn: 163810
* Add a new compression type to ModRM table that detects when the memory modRM ↵Craig Topper2012-09-132-0/+9
| | | | | | byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren. llvm-svn: 163774
* Don't fold indexed loads into TCRETURNmi64.Jakob Stoklund Olesen2012-09-133-1/+39
| | | | | | | | | | | | | We don't have enough GR64_TC registers when calling a varargs function with 6 arguments. Since %al holds the number of vector registers used, only %r11 is available as a scratch register. This means that addressing modes using both base and index registers can't be folded into TCRETURNmi64. <rdar://problem/12282281> llvm-svn: 163761
* Fix PR11985Michael Liao2012-09-122-15/+26
| | | | | | | | | | | - BlockAddress has no support of BA + offset form and there is no way to propagate that offset into machine operand; - Add BA + offset support and a new interface 'getTargetBlockAddress' to simplify target block address forming; - All targets are modified to use new interface and X86 backend is enhanced to support BA + offset addressing. llvm-svn: 163743
* [ms-inline asm] Make the operand size directives case insensitive.Chad Rosier2012-09-121-8/+9
| | | | llvm-svn: 163729
* Add support for AMD Geode.Roman Divacky2012-09-121-0/+1
| | | | llvm-svn: 163710
* Indentation fixes. No functional change.Craig Topper2012-09-121-8/+8
| | | | llvm-svn: 163682
* Release build: guard dump functions withManman Ren2012-09-112-2/+2
| | | | | | | | "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163339. llvm-svn: 163653
* StringSwitchify.Chad Rosier2012-09-111-8/+10
| | | | llvm-svn: 163649
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