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* Allow x87 FP registers to be alive globally in a function.Jakob Stoklund Olesen2010-07-162-37/+389
| | | | | | | | | | | | | | | | FP_REG_KILL instructions are still inserted, but can be disabled by passing -live-x87 to llc. The X87FPRegKillInserterPass is going to be removed shortly. CFG edges are partioned into bundles where the x87 stack must be allocated identically. Code is insertad at the end of each basic block that shuffles the live FP registers to match the outgoing bundles expectations. This fix is in preparation for some upcoming register allocator improvements that may extend the live range of registers beyond a basic block, similar to LICM. It also provides a nice runtime speedup if you are building with -mfpmath=387. llvm-svn: 108529
* Split -enable-finite-only-fp-math to two options:Evan Cheng2010-07-151-10/+5
| | | | | | -enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN. llvm-svn: 108465
* fix the encoding of MMX_MOVFR642Qrr, it starts with 0xF2 not 0xF3,Chris Lattner2010-07-151-1/+1
| | | | | | | | this fixes rdar://8192860. Unfortunately it can only be triggered with llc because llvm-mc matches another (correctly encoded) version of this, so no testcase. llvm-svn: 108454
* Last COPY conversion.Jakob Stoklund Olesen2010-07-141-3/+2
| | | | llvm-svn: 108387
* Use TargetOpcode::COPY instead of X86-native register copy instructions whenJakob Stoklund Olesen2010-07-142-30/+27
| | | | | | | lowering atomics. This will allow those copies to still be coalesced after TII::isMoveInstr is removed. llvm-svn: 108385
* fix indentationChris Lattner2010-07-141-9/+7
| | | | llvm-svn: 108368
* Don't pass StringRef by reference.Benjamin Kramer2010-07-141-2/+2
| | | | llvm-svn: 108366
* Merge lib/Target/X86/X86COFF.h into include/llvm/Support/COFF.h,Chris Lattner2010-07-142-100/+8
| | | | | | patch by Michael Spencer! llvm-svn: 108342
* Fix for PR7193 was overly conservative. The only case where sibcall calleeEvan Cheng2010-07-141-6/+12
| | | | | | | | | | address cannot be allocated a register is in 32-bit mode where the first three arguments are marked inreg. In that case EAX, EDX, and ECX will be used for argument passing. This fixes PR7610. llvm-svn: 108327
* Don't propagate debug locations to instructions for materializingDan Gohman2010-07-141-1/+1
| | | | | | | constants, since they may not be emited near the other instructions which get the same line, and this confuses debug info. llvm-svn: 108302
* Add AVX 256-bit compare instructions and a bunch of testcasesBruno Cardoso Lopes2010-07-131-0/+10
| | | | llvm-svn: 108286
* AVX 256-bit conversion instructionsBruno Cardoso Lopes2010-07-134-15/+105
| | | | | | Add the x86 VEX_L form to handle special cases where VEX_L must be set. llvm-svn: 108274
* Added a check that pusha cannot be encoded in 64-bit mode.Kevin Enderby2010-07-131-0/+2
| | | | llvm-svn: 108265
* my work on adding segment registers to LEA missed the Chris Lattner2010-07-131-12/+3
| | | | | | | disassembler. Remove some code from the disassembler to compensate, unbreaking disassembly of lea's. llvm-svn: 108226
* Add AVX 256-bit packed logical formsBruno Cardoso Lopes2010-07-131-0/+19
| | | | llvm-svn: 108224
* Add AVX 256-bit unop arithmetic instructionsBruno Cardoso Lopes2010-07-131-53/+86
| | | | llvm-svn: 108223
* Since AVX is a superset of all SSE versions, only use HasAVX for AVX ↵Bruno Cardoso Lopes2010-07-132-81/+77
| | | | | | instructions llvm-svn: 108222
* Move some SIMD fragment code into X86InstrFragmentsSIMD so that theDavid Greene2010-07-122-336/+336
| | | | | | | utility classes can be used from multiple files. This will aid transitioning to a new refactored x86 SIMD specification. llvm-svn: 108213
* Add AVX 256 binary arithmetic instructionsBruno Cardoso Lopes2010-07-121-7/+23
| | | | llvm-svn: 108207
* More refactoring of basic SSE arith instructions. Open room for 256-bit ↵Bruno Cardoso Lopes2010-07-121-207/+158
| | | | | | instructions llvm-svn: 108204
* Apply the SSE dependence idiom for SSE unary operations toDan Gohman2010-07-121-2/+8
| | | | | | | SD instructions too, in addition to SS instructions. And add a comment about it. llvm-svn: 108191
* Add AVX 256-bit MOVMSK formsBruno Cardoso Lopes2010-07-121-0/+6
| | | | llvm-svn: 108184
* Check begin!=end, rather than !begin.Dan Gohman2010-07-121-2/+2
| | | | llvm-svn: 108167
* Don't fast-isel an x87 comparison opcode, as fast-isel doesn'tDan Gohman2010-07-121-2/+2
| | | | | | support branching on x87 comparisons yet. This fixes PR7624. llvm-svn: 108149
* Convert getLoadStoreRegOpcode to use a switch.Rafael Espindola2010-07-121-26/+29
| | | | llvm-svn: 108123
* A basic block that only uses RFP registers still needs the FP_REG_KILL marker.Jakob Stoklund Olesen2010-07-121-10/+7
| | | | | | This fixes PR7375. llvm-svn: 108120
* Convert the last getPhysicalRegisterRegClass in VirtRegRewriter.cpp toRafael Espindola2010-07-121-1/+2
| | | | | | | | | getMinimalPhysRegClass. It was used to produce spills, and it is better to use the most specific class if possible. Update getLoadStoreRegOpcode to handle GR32_AD. llvm-svn: 108115
* Use target independent COPY instructions for the fake fextend and froundJakob Stoklund Olesen2010-07-111-6/+6
| | | | | | operations in x87 code. llvm-svn: 108098
* Remove obsolete README_SSE note.Jakob Stoklund Olesen2010-07-111-10/+0
| | | | | | | | | | | | | | | We are generating movaps for all XMM register copies, including scalar floating point values. This is known to be at least as good as movss and movsd for all known architectures up to and including Nehalem because it avoids a partial register stall. The SSEDomainFix pass will switch movaps to movdqa when appropriate (i.e., when operands come from the integer unit). We don't now that switching movaps to movapd has any benefit. The same applies to andps -> pand. llvm-svn: 108096
* Avoid SSE instructions in FastIsel when it is not available.Jakob Stoklund Olesen2010-07-111-4/+4
| | | | llvm-svn: 108091
* X86InstrInfo::copyRegToReg is dead. Long live copyPhysReg!Jakob Stoklund Olesen2010-07-112-171/+0
| | | | llvm-svn: 108076
* Use COPY in X86FastISel::X86SelectRet.Jakob Stoklund Olesen2010-07-111-6/+4
| | | | | | | Don't try a cross-class copy. That is very unlikely anywy since return value registers are usually register class friendly. (%EAX, %XMM0, etc). llvm-svn: 108074
* Use COPY in FastISel everywhere it is safe and trivial.Jakob Stoklund Olesen2010-07-111-18/+8
| | | | | | | The remaining copyRegToReg calls actually check the return value (shock!), so we cannot trivially replace them with COPY instructions. llvm-svn: 108069
* Don't emit st(0)/st(1) copies as FpMOV instructions. Use FpSET_ST? instead.Jakob Stoklund Olesen2010-07-102-83/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on a patch by Rafael Espíndola. Attempt to make the FpSET_ST1 hack more robust, but we are still relying on FpSET_ST0 preceeding it. This is only for supporting really weird x87 inline asm. We support: FpSET_ST0 INLINEASM FpSET_ST0 FpSET_ST1 INLINEASM with and without kills on the arguments. We don't support: FpSET_ST1 FpSET_ST0 INLINEASM nor FpSET_ST1 INLINEASM Just Don't Do It! llvm-svn: 108047
* Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman2010-07-106-89/+298
| | | | | | | | | - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
* An x86 function returns a floating point value in st(0), and we must make sureJakob Stoklund Olesen2010-07-101-18/+26
| | | | | | | | | it is popped, even if it is ununsed. A CopyFromReg node is too weak to represent the required sideeffect, so insert an FpGET_ST0 instruction directly instead. This will matter when CopyFromReg gets lowered to a generic COPY instruction. llvm-svn: 108037
* Declare YMM subregisters in the right way! Thanks JakobBruno Cardoso Lopes2010-07-091-2/+1
| | | | llvm-svn: 108022
* Add AVX 256-bit packed MOVNT variantsBruno Cardoso Lopes2010-07-091-0/+22
| | | | llvm-svn: 108021
* Remember the *_TC opcodes for load/storeJakob Stoklund Olesen2010-07-091-0/+4
| | | | llvm-svn: 108020
* Add AVX 256-bit unpack and interleaveBruno Cardoso Lopes2010-07-091-0/+17
| | | | llvm-svn: 108017
* Automatically fold COPY instructions into stack load/store.Jakob Stoklund Olesen2010-07-091-1/+1
| | | | llvm-svn: 108012
* Fix a few testsJakob Stoklund Olesen2010-07-091-1/+1
| | | | llvm-svn: 108011
* Start the support for AVX instructions with 256-bit %ymm registers. A couple ofBruno Cardoso Lopes2010-07-098-18/+99
| | | | | | | | | | | | | | | notes: - The instructions are being added with dummy placeholder patterns using some 256 specifiers, this is not meant to work now, but since there are some multiclasses generic enough to accept them, when we go for codegen, the stuff will be already there. - Add VEX encoding bits to support YMM - Add MOVUPS and MOVAPS in the first round - Use "Y" as suffix for those Instructions: MOVUPSYrr, ... - All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX file. llvm-svn: 107996
* --- Reverse-merging r107947 into '.':Bob Wilson2010-07-093-202/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h llvm-svn: 107987
* Merge VEX enums with other x86 enum forms. Also fix all checks of which VEXBruno Cardoso Lopes2010-07-092-22/+17
| | | | | | fields to use. llvm-svn: 107952
* Fix the memoperand offsets in code generated for va_start.Dan Gohman2010-07-091-3/+3
| | | | llvm-svn: 107948
* have the mc lowering process handle a few tail call forms, lowering them toChris Lattner2010-07-093-13/+19
| | | | | | | | | | | | | jumps where possible and turning the TAILCALL marker in the instruction asm string into a proper comment. This eliminates a FIXME and is on the path to finishing: rdar://7639610 - eliminate encoding and asm info for TAILJMPd TAILJMPr TAILJMPn, etc. However, I can't eliminate the encodings for these instructions because the JIT still exists and has its own copy of the encoder, sigh. llvm-svn: 107946
* Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emittingDan Gohman2010-07-093-65/+202
| | | | | | a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL. llvm-svn: 107943
* Factor out x86 segment override prefix encoding, and also use it for VEXBruno Cardoso Lopes2010-07-091-18/+33
| | | | llvm-svn: 107942
* reject pseudo instructions early in the encoder.Chris Lattner2010-07-092-11/+5
| | | | llvm-svn: 107939
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