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* [globalisel][tablegen] Move <Target>InstructionSelector declarations to ↵Daniel Sanders2017-04-061-3/+1
| | | | | | | | | | | | | | | | anonymous namespaces Summary: This resolves the issue of tablegen-erated includes in the headers for non-GlobalISel builds in a simpler way than before. Reviewers: qcolombet, ab Reviewed By: ab Subscribers: igorb, ab, mgorny, dberris, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30998 llvm-svn: 299637
* [GlobalISel][X86] support G_FRAME_INDEX instruction selection.Igor Breger2017-03-261-1/+1
| | | | | | | | | | | | | | | Summary: Support G_FRAME_INDEX instruction selection. Reviewers: zvi, rovka, ab, qcolombet Reviewed By: ab Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank Differential Revision: https://reviews.llvm.org/D30980 llvm-svn: 298800
* [X86] Remove extra semicolon to placate GCC. NFCI.Davide Italiano2017-03-211-1/+1
| | | | llvm-svn: 298423
* ExecutionDepsFix: Let targets specialize the pass; NFCMatthias Braun2017-03-181-2/+18
| | | | | | | | Let targets specialize the pass with the register class so we can get a parameterless default constructor and can put the pass into the pass registry to enable testing with -run-pass=. llvm-svn: 298184
* ExecutionDepsFix: Normalize names; NFCMatthias Braun2017-03-181-1/+1
| | | | | | | Normalize ExeDepsFix, execution-fix, ExecutionDependencyFix and ExecutionDepsFix to the last one. llvm-svn: 298183
* [GlobalISel] Fix compiler warnings and make assert assert something.Benjamin Kramer2017-02-221-1/+1
| | | | llvm-svn: 295827
* [X86][GlobalISel] Initial implementation , select G_ADD gpr, gprIgor Breger2017-02-221-3/+6
| | | | | | | | | | | | | | Summary: Initial implementation for X86InstructionSelector. Handle selection COPY and G_ADD/G_SUB gpr, gpr . Reviewers: qcolombet, rovka, zvi, ab Reviewed By: rovka Subscribers: mgorny, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29816 llvm-svn: 295824
* add #ifdef, fix compilation error in case LLVM_BUILD_GLOBAL_ISEL=OFFIgor Breger2017-02-101-0/+2
| | | | llvm-svn: 294726
* [X86][GlobalISel] Add general-purpose Register BankIgor Breger2017-02-101-12/+20
| | | | | | | | | | | | | | | | | Summary: [X86][GlobalISel] Add general-purpose Register Bank. Add trivial handling of G_ADD legalization . Add Regestry Bank selection for COPY and G_ADD instructions Reviewers: rovka, zvi, ab, t.p.northover, qcolombet Reviewed By: qcolombet Subscribers: qcolombet, mgorny, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29771 llvm-svn: 294723
* Temporarily revert "For X86-64 linux and PPC64 linux align int128 to 16 bytes."Eric Christopher2017-02-101-5/+0
| | | | | | | | | until we can get better TargetMachine::isCompatibleDataLayout to compare - otherwise we can't code generate existing bitcode without a string equality data layout. This reverts commit r294702. llvm-svn: 294709
* For X86-64 linux and PPC64 linux align int128 to 16 bytes.Eric Christopher2017-02-101-0/+5
| | | | | | | | | | | | For other platforms we should find out what they need and likely make the same change, however, a smaller additional change is easier for platforms we know have it specified in the ABI. As part of this rewrite some of the handling in the backends for data layout and update a bunch of testcases. Based on a patch by Simonas Kazlauskas! llvm-svn: 294702
* [X86] Fix some Clang-tidy modernize and Include What You Use warnings; other ↵Eugene Zelenko2017-02-021-17/+44
| | | | | | minor fixes (NFC). llvm-svn: 293949
* [CodeGen] Move MacroFusion to the targetEvandro Menezes2017-02-011-1/+2
| | | | | | | | | | | | | This patch moves the class for scheduling adjacent instructions, MacroFusion, to the target. In AArch64, it also expands the fusion to all instructions pairs in a scheduling block, beyond just among the predecessors of the branch at the end. Differential revision: https://reviews.llvm.org/D28489 llvm-svn: 293737
* This is a large patch for X86 AVX-512 of an optimization for reducing code ↵Gadi Haber2016-12-281-0/+2
| | | | | | | | | | | | size by encoding EVEX AVX-512 instructions using the shorter VEX encoding when possible. There are cases of AVX-512 instructions that have two possible encodings. This is the case with instructions that use vector registers with low indexes of 0 - 15 and do not use the zmm registers or the mask k registers. The EVEX encoding prefix requires 4 bytes whereas the VEX prefix can take only up to 3 bytes. Consequently, using the VEX encoding for these instructions results in a code size reduction of ~2 bytes even though it is compiled with the AVX-512 features enabled. Reviewers: Craig Topper, Zvi Rackoover, Elena Demikhovsky Differential Revision: https://reviews.llvm.org/D27901 llvm-svn: 290663
* [GlobalISel] Drop workaround for Legalizer member/class sharing a name. NFC.Ahmed Bougacha2016-12-151-1/+1
| | | | | | | | MachineLegalizer used to be the name of both the class and the member, causing GCC errors. r276522 fixed that by renaming the member to just 'Legalizer'. The 'class' workaround isn't necessary anymore; drop it. llvm-svn: 289848
* MachineScheduler: Export function to construct "default" scheduler.Matthias Braun2016-11-281-0/+8
| | | | | | | | | | | | | | | | | | This makes the createGenericSchedLive() function that constructs the default scheduler available for the public API. This should help when you want to get a scheduler and the default list of DAG mutations. This also shrinks the list of default DAG mutations: {Load|Store}ClusterDAGMutation and MacroFusionDAGMutation are no longer added by default. Targets can easily add them if they need them. It also makes it easier for targets to add alternative/custom macrofusion or clustering mutations while staying with the default createGenericSchedLive(). It also saves the callback back and forth in TargetInstrInfo::enableClusterLoads()/enableClusterStores(). Differential Revision: https://reviews.llvm.org/D26986 llvm-svn: 288057
* [X86][GlobalISel] Add minimal call lowering support to the IRTranslatorZvi Rackover2016-11-151-1/+63
| | | | | | | | | | | | | | | Summary: Add basic functionality to support call lowering for X86. Currently only supports functions which return void and take zero arguments. Inspired by commit 286573. Reviewers: ab, qcolombet, t.p.northover Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26593 llvm-svn: 286935
* Add a pass to optimize patterns of vectorized interleaved memory accesses forDavid L Kreitzer2016-10-141-0/+3
| | | | | | | | | | | | | X86. The pass optimizes as a unit the entire wide load + shuffles pattern produced by interleaved vectorization. This initial patch optimizes one pattern (64-bit elements interleaved by a factor of 4). Future patches will generalize to additional patterns. Patch by Farhana Aleen Differential revision: http://reviews.llvm.org/D24681 llvm-svn: 284260
* Move the global variables representing each Target behind accessor functionMehdi Amini2016-10-091-2/+2
| | | | | | | | This avoids "static initialization order fiasco" Differential Revision: https://reviews.llvm.org/D25412 llvm-svn: 283702
* [Triple] Add triple for FuchsiaPetr Hosek2016-10-061-0/+2
| | | | | | | | Fuchsia is a new operating system. Differential Revision: https://reviews.llvm.org/D25116 llvm-svn: 283419
* [Target] move reciprocal estimate settings from TargetOptions to TargetLoweringSanjay Patel2016-10-041-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | The motivation for the change is that we can't have pseudo-global settings for codegen living in TargetOptions because that doesn't work with LTO. Ideally, these reciprocal attributes will be moved to the instruction-level via FMF, metadata, or something else. But making them function attributes is at least an improvement over the current state. The ingredients of this patch are: Remove the reciprocal estimate command-line debug option. Add TargetRecip to TargetLowering. Remove TargetRecip from TargetOptions. Clean up the TargetRecip implementation to work with this new scheme. Set the default reciprocal settings in TargetLoweringBase (everything is off). Update the PowerPC defaults, users, and tests. Update the x86 defaults, users, and tests. Note that if this patch needs to be reverted, the related clang patch checked in at r283251 should be reverted too. Differential Revision: https://reviews.llvm.org/D24816 llvm-svn: 283252
* [CodeGen] Add support for emitting .init_array instead of .ctors on FreeBSD.Davide Italiano2016-09-261-0/+2
| | | | | PR: 30494 llvm-svn: 282451
* Remove the default subtarget from the x86 port as it isn't necessary (orEric Christopher2016-09-201-2/+1
| | | | | | correct) anymore. llvm-svn: 282031
* Remove a use of subtarget initialization in the X86 backend so we can get ↵Eric Christopher2016-09-201-1/+4
| | | | | | | | rid of the default subtarget. NFC intended. llvm-svn: 281982
* [AVX512] Add initial support for the Execution Domain fixing pass to change ↵Craig Topper2016-07-221-1/+1
| | | | | | some EVEX instructions. llvm-svn: 276393
* Don't optimize movs to pushes in -O0 builds.Nico Weber2016-07-141-1/+1
| | | | | | https://reviews.llvm.org/D22362 llvm-svn: 275431
* Delete some trailing whitespace.Nico Weber2016-07-141-2/+2
| | | | llvm-svn: 275429
* [X86] Disable FixupSetCC for CodeGenOpt::NoneMichael Kuperstein2016-07-111-4/+4
| | | | | | | | | | It is an optimization pass, and should not run at -O0. Especially since Fast RA will not do the required register coalescing anyway, so it's a loss even from the optimization standpoint. This also works around (but doesn't quite fix) PR28489. llvm-svn: 275099
* Recommit r274692 - [X86] Transform setcc + movzbl into xorl + setccMichael Kuperstein2016-07-071-1/+2
| | | | | | | | | | | xorl + setcc is generally the preferred sequence due to the partial register stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller. This fixes PR28146. The original commit tried inserting an 8bit-subreg into a GR32 (not GR32_ABCD) which was not appreciated by fast regalloc on 32-bit. llvm-svn: 274802
* Revert r274692 to check whether this is what breaks windows selfhost.Michael Kuperstein2016-07-071-2/+1
| | | | llvm-svn: 274771
* [X86] Transform setcc + movzbl into xorl + setccMichael Kuperstein2016-07-061-1/+2
| | | | | | | | | | | xorl + setcc is generally the preferred sequence due to the partial register stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller. This fixes PR28146. Differential Revision: http://reviews.llvm.org/D21774 llvm-svn: 274692
* Address post-review for r270246David Majnemer2016-05-201-11/+13
| | | | | | | | | This gets rid of some unnecessary SmallStrings in X86TargetMachine::getSubtargetImpl. No functionality change is intended. llvm-svn: 270270
* [X86] Reduce memory allocations in X86TargetMachine::getSubtargetImplDavid Majnemer2016-05-201-7/+12
| | | | | | | | We performed a number of memory allocations each time getTTI was called, remove them by using SmallString. No functionality change intended. llvm-svn: 270246
* Delete Reloc::Default.Rafael Espindola2016-05-181-4/+40
| | | | | | | | | | | | Having an enum member named Default is quite confusing: Is it distinct from the others? This patch removes that member and instead uses Optional<Reloc> in places where we have a user input that still hasn't been maped to the default value, which is now clear has no be one of the remaining 3 options. llvm-svn: 269988
* Re-commit r269828 "X86: Avoid using _chkstk when lowering WIN_ALLOCA ↵Hans Wennborg2016-05-181-0/+1
| | | | | | | | | | | | instructions" with an additional fix to make RegAllocFast ignore undef physreg uses. It would previously get confused about the "push %eax" instruction's use of eax. That method for adjusting the stack pointer is used in X86FrameLowering::emitSPUpdate as well, but since that runs after register-allocation, we didn't run into the RegAllocFast issue before. llvm-svn: 269949
* Trivial cleanups.Rafael Espindola2016-05-181-1/+1
| | | | | | | This just clang formats and cleans comments in an area I am about to post a patch for review. llvm-svn: 269946
* Revert r269828 "X86: Avoid using _chkstk when lowering WIN_ALLOCA instructions"Hans Wennborg2016-05-171-1/+0
| | | | | | Seems to have broken the Windows ASan bot. Reverting while investigating. llvm-svn: 269833
* X86: Avoid using _chkstk when lowering WIN_ALLOCA instructionsHans Wennborg2016-05-171-0/+1
| | | | | | | | | | | | | | | This patch moves the expansion of WIN_ALLOCA pseudo-instructions into a separate pass that walks the CFG and lowers the instructions based on a conservative estimate of the offset between the stack pointer and the lowest accessed stack address. The goal is to reduce binary size and run-time costs by removing calls to _chkstk. While it doesn't fix all the code quality problems with inalloca calls, it's an incremental improvement for PR27076. Differential Revision: http://reviews.llvm.org/D20263 llvm-svn: 269828
* CodeGen: Move TargetPassConfig from Passes.h to an own header; NFCMatthias Braun2016-05-101-0/+1
| | | | | | | | Many files include Passes.h but only a fraction needs to know about the TargetPassConfig class. Move it into an own header. Also rename Passes.cpp to TargetPassConfig.cpp while we are at it. llvm-svn: 269011
* [X86] Register and initialize the FixupBW pass.Ahmed Bougacha2016-05-071-0/+1
| | | | | | That lets us use it in MIR tests. llvm-svn: 268830
* Remove HasFnAttribute guards to getFnAttribute callsNirav Dave2016-03-301-1/+0
| | | | | | | | | | | | These checks are redundant and can be removed Reviewers: hans Subscribers: llvm-commits, mzolotukhin Differential Revision: http://reviews.llvm.org/D18564 llvm-svn: 264872
* [PS4] Guarantee an instruction after a 'noreturn' call.Paul Robinson2016-03-241-1/+3
| | | | | | | | | | We need the "return address" of a noreturn call to be within the bounds of the calling function; TrapUnreachable turns 'unreachable' into a 'ud2' instruction, which has that desired effect. Differential Revision: http://reviews.llvm.org/D18414 llvm-svn: 264224
* [X86] New pass to change byte and word instructions to zero-extending versions.Kevin B. Smith2016-02-111-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D17032 llvm-svn: 260572
* [X86] Fix stack alignment for MCU target, by Anton Nadolskiy.Andrey Turetskiy2016-02-101-2/+7
| | | | | | | | This patch fixes stack alignments for MCU (should be aligned to 4 bytes). Differential Revision: http://reviews.llvm.org/D15646 llvm-svn: 260375
* Revert r259576: Disable the vzeroupper insertion pass on PS4.Yunzhong Gao2016-02-031-3/+0
| | | | | | Will re-implement based on review feedback. llvm-svn: 259615
* Disable the vzeroupper insertion pass on PS4.Yunzhong Gao2016-02-021-0/+3
| | | | | | | | See comments in test/CodeGen/X86/avx-vzeroupper.ll for more explanation. Original patch by: Sean Silva llvm-svn: 259576
* LEA code size optimization pass (Part 1): Remove redundant address ↵Alexey Bataev2015-12-041-0/+3
| | | | | | | | | recalculations, by Andrey Turetsky Add new x86 pass which replaces address calculations in load or store instructions with def register of existing LEA (must be in the same basic block), if the LEA calculates address that differs only by a displacement. Works only with -Os or -Oz. Differential Revision: http://reviews.llvm.org/D13294 llvm-svn: 254712
* Revert "Revert "Revert r248959, "[WinEH] Emit int3 after noreturn calls on ↵Reid Kleckner2015-10-091-0/+7
| | | | | | | | | | Win64""" This reverts commit r249794. Apparently my checkouts are full of unexpected surprises today. llvm-svn: 249796
* Revert "Revert r248959, "[WinEH] Emit int3 after noreturn calls on Win64""Reid Kleckner2015-10-091-7/+0
| | | | | | | | This reverts commit r249032. TODO write commit msg llvm-svn: 249794
* Revert r248959, "[WinEH] Emit int3 after noreturn calls on Win64"NAKAMURA Takumi2015-10-011-0/+7
| | | | | | It broke; LLVM :: CodeGen__Generic__2009-11-16-BadKillsCrash.ll llvm-svn: 249032
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