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* Enable MachineVerifier in debug mode for X86, ARM, AArch64, Mips.Matthias Braun2014-12-111-3/+3
| | | | llvm-svn: 224075
* [CodeGen] Add print and verify pass after each MachineFunctionPass by defaultMatthias Braun2014-12-111-23/+9
| | | | | | | | | | | | | | | | | | | Previously print+verify passes were added in a very unsystematic way, which is annoying when debugging as you miss intermediate steps and allows bugs to stay unnotice when no verification is performed. To make this change practical I added the possibility to explicitely disable verification. I used this option on all places where no verification was performed previously (because alot of places actually don't pass the MachineVerifier). In the long term these problems should be fixed properly and verification enabled after each pass. I'll enable some more verification in subsequent commits. This is the 2nd attempt at this after realizing that PassManager::add() may actually delete the pass. llvm-svn: 224059
* This reverts commit r224043 and r224042.Rafael Espindola2014-12-111-6/+20
| | | | | | check-llvm was failing. llvm-svn: 224045
* Enable machineverifier in debug mode for X86, ARM, AArch64, MipsMatthias Braun2014-12-111-3/+3
| | | | llvm-svn: 224043
* [CodeGen] Add print and verify pass after each MachineFunctionPass by defaultMatthias Braun2014-12-111-23/+9
| | | | | | | | | | | | | | | | Previously print+verify passes were added in a very unsystematic way, which is annoying when debugging as you miss intermediate steps and allows bugs to stay unnotice when no verification is performed. To make this change practical I added the possibility to explicitely disable verification. I used this option on all places where no verification was performed previously (because alot of places actually don't pass the MachineVerifier). In the long term these problems should be fixed properly and verification enabled after each pass. I'll enable some more verification in subsequent commits. llvm-svn: 224042
* Add out of line virtual destructors to all LLVMTargetMachine subclassesReid Kleckner2014-11-201-2/+2
| | | | | | | | | | | | | | | | | These recently all grew a unique_ptr<TargetLoweringObjectFile> member in r221878. When anyone calls a virtual method of a class, clang-cl requires all virtual methods to be semantically valid. This includes the implicit virtual destructor, which triggers instantiation of the unique_ptr destructor, which fails because the type being deleted is incomplete. This is just part of the ongoing saga of PR20337, which is affecting Blink as well. Because the MSVC ABI doesn't have key functions, we end up referencing the vtable and implicit destructor on any virtual call through a class. We don't actually end up emitting the dtor, so it'd be good if we could avoid this unneeded type completion work. llvm-svn: 222480
* This patch changes the ownership of TLOF from TargetLoweringBase to ↵Aditya Nandakumar2014-11-131-0/+20
| | | | | | TargetMachine so that different subtargets could share the TLOF effectively llvm-svn: 221878
* Add subtarget caches to aarch64, arm, ppc, and x86.Eric Christopher2014-10-061-0/+40
| | | | | | | | | These will make it easier to test further changes to the code generation and optimization pipelines as those are moved to subtargets initialized with target feature and target cpu. llvm-svn: 219106
* [X86] Use the generic AtomicExpandPass instead of X86AtomicExpandPassRobin Morisset2014-09-171-1/+1
| | | | | | | | | | | | This required a new hook called hasLoadLinkedStoreConditional to know whether to expand atomics to LL/SC (ARM, AArch64, in a future patch Power) or to CmpXchg (X86). Apart from that, the new code in AtomicExpandPass is mostly moved from X86AtomicExpandPass. The main result of this patch is to get rid of that pass, which had lots of code duplicated with AtomicExpandPass. llvm-svn: 217928
* Reinstate "Nuke the old JIT."Eric Christopher2014-09-021-7/+0
| | | | | | | | Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reinstates commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 216982
* Move some X86 subtarget configuration onto the subtarget that's beingEric Christopher2014-08-091-20/+0
| | | | | | created. llvm-svn: 215271
* Temporarily Revert "Nuke the old JIT." as it's not quite ready toEric Christopher2014-08-071-0/+7
| | | | | | | | | | | be deleted. This will be reapplied as soon as possible and before the 3.6 branch date at any rate. Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reverts commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 215154
* Nuke the old JIT.Rafael Espindola2014-08-071-7/+0
| | | | | | | | | I am sure we will be finding bits and pieces of dead code for years to come, but this is a good start. Thanks to Lang Hames for making MCJIT a good replacement! llvm-svn: 215111
* X86: expand atomics in IR instead of as MachineInstrs.Tim Northover2014-07-011-0/+7
| | | | | | | | | | | | The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
* Move all of the x86 subtarget initialized variables down into the x86 subtargetEric Christopher2014-06-091-44/+1
| | | | | | from the x86 target machine. Should be no functional change. llvm-svn: 210479
* X86: simplify data layout calculationSaleem Abdulrasool2014-06-081-3/+2
| | | | | | | | X86Subtarget::isTargetCygMing || X86Subtarget::isTargetKnownWindowsMSVC is equivalent to all Windows environments. Simplify the check to isOSWindows. NFC. llvm-svn: 210431
* Replace the use of TargetMachine with a tiny bool variable.Eric Christopher2014-06-061-1/+1
| | | | llvm-svn: 210386
* Remove all local variables from X86SelectionDAGInfo, the DAG hasEric Christopher2014-06-061-1/+1
| | | | | | all of the ones we were stashing away on startup. llvm-svn: 210385
* Remove X86Subtarget from the X86FrameLowering constructor sinceEric Christopher2014-06-051-11/+9
| | | | | | | we can just pass in the values we already know and we're not caching the subtarget anymore. llvm-svn: 210292
* Remove duplicate copy of InstrItineraryData from the TargetMachine,Eric Christopher2014-06-051-1/+0
| | | | | | it's already on the subtarget. llvm-svn: 210289
* Remove uses of the TargetMachine from X86FrameLowering.Eric Christopher2014-06-051-1/+1
| | | | llvm-svn: 210223
* Avoid using subtarget features when adding X86 specific passes toEric Christopher2014-05-221-11/+3
| | | | | | the pass pipeline. llvm-svn: 209382
* Rename createGlobalBaseRegPass -> createX86GlobalBaseRegPass to makeEric Christopher2014-05-221-1/+1
| | | | | | it obvious that it's a target specific pass. llvm-svn: 209380
* Make early if conversion dependent upon the subtarget and addEric Christopher2014-05-211-11/+2
| | | | | | | a subtarget hook to enable. Unconditionally add to the pass pipeline for targets that might want to use it. No functional change. llvm-svn: 209340
* [X86] Tune LEA usage for SilvermontAlexey Volkov2014-05-201-1/+2
| | | | | | | | | | | | | According to Intel Software Optimization Manual on Silvermont in some cases LEA is better to be replaced with ADD instructions: "The rule of thumb for ADDs and LEAs is that it is justified to use LEA with a valid index and/or displacement for non-destructive destination purposes (especially useful for stack offset cases), or to use a SCALE. Otherwise, ADD(s) are preferable." Differential Revision: http://reviews.llvm.org/D3826 llvm-svn: 209198
* Patch by Vadim ChugunovYaron Keren2014-04-191-0/+7
| | | | | | | | | | | Win64 stack unwinder gets confused when execution flow "falls through" after a call to 'noreturn' function. This fixes the "missing epilogue" problem by emitting a trap instruction for IR 'unreachable' on x86_x64-pc-windows. A secondary use for it would be for anyone wanting to make double-sure that 'noreturn' functions, indeed, do not return. llvm-svn: 206684
* isTargetWindows() renamed to isTargetKnownWindowsMSVC()Yaron Keren2014-04-011-2/+2
| | | | | | | | to reflect its current functionality. Based on Takumi NAKAMURA suggestion. llvm-svn: 205338
* Prune includes in X86 target.Craig Topper2014-03-191-1/+0
| | | | llvm-svn: 204216
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-091-5/+5
| | | | | | class. llvm-svn: 203378
* [x86] Kill gratuitous X86_{32,64}TargetMachine subclasses, use X86TargetMachineDavid Woodhouse2014-01-081-38/+13
| | | | llvm-svn: 198720
* Make the llvm mangler depend only on DataLayout.Rafael Espindola2014-01-031-0/+1
| | | | | | | | | | | | | | Before this patch any program that wanted to know the final symbol name of a GlobalValue had to link with Target. This patch implements a compromise solution where the mangler uses DataLayout. This way, any tool that already links with Target (llc, clang) gets the exact behavior as before and new IR files can be mangled without linking with Target. With this patch the mangler is constructed with just a DataLayout and DataLayout is extended to include the information the Mangler needs. llvm-svn: 198438
* Remove the 's' DataLayout specificationRafael Espindola2014-01-011-4/+0
| | | | | | | | | | | | | | | | | | | | | | | During the years there have been some attempts at figuring out how to align byval arguments. A look at the commit log suggests that they were * Use the ABI alignment. * When that was not sufficient for x86-64, I added the 's' specification to DataLayout. * When that was not sufficient Evan added the virtual getByValTypeAlignment. * When even that was not sufficient, we just got the FE to add the alignment to the byval. This patch is just a simple cleanup that removes my first attempt at fixing the problem. I also added an AArch64 implementation of getByValTypeAlignment to make sure this patch is a nop. I also left the 's' parsing for backward compatibility. I will send a short email to llvmdev about the change for anyone maintaining an out of tree target. llvm-svn: 198287
* Synchronize the NaCl DataLayout strings with the ones in clang.Rafael Espindola2013-12-191-2/+5
| | | | | | Patch by Derek Schuff. llvm-svn: 197640
* One last cleanup of LLVM's DataLayout strings.Rafael Espindola2013-12-161-5/+4
| | | | | | | Produce them in the same order on every target. The order is that of getStringRepresentation: e|E-i*-f*-v*-a*-s*-n*-S*. llvm-svn: 197411
* The preferred alignment defaults to the abi alignment. Omit if it is the same.Rafael Espindola2013-12-161-3/+3
| | | | llvm-svn: 197400
* On DataLayout, omit the default of p:64:64:64.Rafael Espindola2013-12-161-3/+1
| | | | llvm-svn: 197397
* Assume defaults to produce smaller datalayout strings.Rafael Espindola2013-12-131-5/+2
| | | | llvm-svn: 197249
* Refactor the computation of the x86 datalayout.Rafael Espindola2013-12-101-14/+47
| | | | llvm-svn: 196976
* Mark some command line flags as hiddenNadav Rotem2013-10-181-2/+2
| | | | llvm-svn: 193013
* X86TargetMachine.cpp: Clarify to emit GOT in i686-{cygming|win32}-elf for mcjit.NAKAMURA Takumi2013-08-211-1/+1
| | | | | | I suppose all "lli -use-mcjit i686-*" should require GOT, (and to fail.) llvm-svn: 188856
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-191-1/+1
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184349
* Remove the MachineMove class.Rafael Espindola2013-05-131-0/+2
| | | | | | | | | | | | It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. llvm-svn: 181680
* This patch adds the X86FixupLEAs pass, which will reduce instructionPreston Gurd2013-04-251-0/+5
| | | | | | | | latency for certain models of the Intel Atom family, by converting instructions into their equivalent LEA instructions, when it is both useful and possible to do so. llvm-svn: 180573
* In this patch, we teach X86_64TargetMachine that it has a ILP32Eli Bendersky2013-01-251-2/+6
| | | | | | | | | | | | | | | | | | | | | (defined by the x32 ABI) mode, in which case its pointers are 32-bits in size. This knowledge is also added to X86RegisterInfo that now returns the appropriate registers in getPointerRegClass. There are many outcomes to this change. In order to keep the patches separate and manageable, we start by focusing on some simple testable cases. The patch adds a test with passing a pointer to a function - focusing on the difference between the two data models for x86-64. Another test is added for handling of 'sret' arguments (and functionality is added in X86ISelLowering to make it work). A note on naming: the "x32 ABI" document refers to the AMD64 architecture (in LLVM it's distinguished by being is64Bits() in the x86 subtarget) with two variations: the LP64 (default) data model, and the ILP32 data model. This patch adds predicates to the subtarget which are consistent with this naming scheme. llvm-svn: 173503
* Provide a place for targets to insert ILP optimization passes.Jakob Stoklund Olesen2013-01-171-6/+10
| | | | | | | | | | | | | | Move the early if-conversion pass into this group. ILP optimizations usually need to find the right balance between register pressure and ILP using the MachineTraceMetrics analysis to identify critical paths and estimate other costs. Such passes should run together so they can share dominator tree and loop info analyses. Besides if-conversion, future passes to run here here could include expression height reduction and ARM's MLxExpansion pass. llvm-svn: 172687
* Pad Short Functions for Intel AtomPreston Gurd2013-01-081-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | The current Intel Atom microarchitecture has a feature whereby when a function returns early then it is slightly faster to execute a sequence of NOP instructions to wait until the return address is ready, as opposed to simply stalling on the ret instruction until the return address is ready. When compiling for X86 Atom only, this patch will run a pass, called "X86PadShortFunction" which will add NOP instructions where less than four cycles elapse between function entry and return. It includes tests. This patch has been updated to address Nadav's review comments - Optimize only at >= O1 and don't do optimization if -Os is set - Stores MachineBasicBlock* instead of BBNum - Uses DenseMap instead of std::map - Fixes placement of braces Patch by Andy Zhang. llvm-svn: 171879
* Switch TargetTransformInfo from an immutable analysis pass that requiresChandler Carruth2013-01-071-4/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a TargetMachine to construct (and thus isn't always available), to an analysis group that supports layered implementations much like AliasAnalysis does. This is a pretty massive change, with a few parts that I was unable to easily separate (sorry), so I'll walk through it. The first step of this conversion was to make TargetTransformInfo an analysis group, and to sink the nonce implementations in ScalarTargetTransformInfo and VectorTargetTranformInfo into a NoTargetTransformInfo pass. This allows other passes to add a hard requirement on TTI, and assume they will always get at least on implementation. The TargetTransformInfo analysis group leverages the delegation chaining trick that AliasAnalysis uses, where the base class for the analysis group delegates to the previous analysis *pass*, allowing all but tho NoFoo analysis passes to only implement the parts of the interfaces they support. It also introduces a new trick where each pass in the group retains a pointer to the top-most pass that has been initialized. This allows passes to implement one API in terms of another API and benefit when some other pass above them in the stack has more precise results for the second API. The second step of this conversion is to create a pass that implements the TargetTransformInfo analysis using the target-independent abstractions in the code generator. This replaces the ScalarTargetTransformImpl and VectorTargetTransformImpl classes in lib/Target with a single pass in lib/CodeGen called BasicTargetTransformInfo. This class actually provides most of the TTI functionality, basing it upon the TargetLowering abstraction and other information in the target independent code generator. The third step of the conversion adds support to all TargetMachines to register custom analysis passes. This allows building those passes with access to TargetLowering or other target-specific classes, and it also allows each target to customize the set of analysis passes desired in the pass manager. The baseline LLVMTargetMachine implements this interface to add the BasicTTI pass to the pass manager, and all of the tools that want to support target-aware TTI passes call this routine on whatever target machine they end up with to add the appropriate passes. The fourth step of the conversion created target-specific TTI analysis passes for the X86 and ARM backends. These passes contain the custom logic that was previously in their extensions of the ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces. I separated them into their own file, as now all of the interface bits are private and they just expose a function to create the pass itself. Then I extended these target machines to set up a custom set of analysis passes, first adding BasicTTI as a fallback, and then adding their customized TTI implementations. The fourth step required logic that was shared between the target independent layer and the specific targets to move to a different interface, as they no longer derive from each other. As a consequence, a helper functions were added to TargetLowering representing the common logic needed both in the target implementation and the codegen implementation of the TTI pass. While technically this is the only change that could have been committed separately, it would have been a nightmare to extract. The final step of the conversion was just to delete all the old boilerplate. This got rid of the ScalarTargetTransformInfo and VectorTargetTransformInfo classes, all of the support in all of the targets for producing instances of them, and all of the support in the tools for manually constructing a pass based around them. Now that TTI is a relatively normal analysis group, two things become straightforward. First, we can sink it into lib/Analysis which is a more natural layer for it to live. Second, clients of this interface can depend on it *always* being available which will simplify their code and behavior. These (and other) simplifications will follow in subsequent commits, this one is clearly big enough. Finally, I'm very aware that much of the comments and documentation needs to be updated. As soon as I had this working, and plausibly well commented, I wanted to get it committed and in front of the build bots. I'll be doing a few passes over documentation later if it sticks. Commits to update DragonEgg and Clang will be made presently. llvm-svn: 171681
* Revert revision 171524. Original message:Nadav Rotem2013-01-051-4/+0
| | | | | | | | | | | | | | | | | | | | URL: http://llvm.org/viewvc/llvm-project?rev=171524&view=rev Log: The current Intel Atom microarchitecture has a feature whereby when a function returns early then it is slightly faster to execute a sequence of NOP instructions to wait until the return address is ready, as opposed to simply stalling on the ret instruction until the return address is ready. When compiling for X86 Atom only, this patch will run a pass, called "X86PadShortFunction" which will add NOP instructions where less than four cycles elapse between function entry and return. It includes tests. Patch by Andy Zhang. llvm-svn: 171603
* The current Intel Atom microarchitecture has a feature whereby when a functionPreston Gurd2013-01-041-0/+4
| | | | | | | | | | | | | | | | | returns early then it is slightly faster to execute a sequence of NOP instructions to wait until the return address is ready, as opposed to simply stalling on the ret instruction until the return address is ready. When compiling for X86 Atom only, this patch will run a pass, called "X86PadShortFunction" which will add NOP instructions where less than four cycles elapse between function entry and return. It includes tests. Patch by Andy Zhang. llvm-svn: 171524
* Fix use-before-construction of X86TargetLowering.Richard Smith2012-12-201-2/+2
| | | | llvm-svn: 170654
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