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* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-2/+2
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Remove the X86 Maximal Stack Alignment Check pass as it is no longer necessary.Chad Rosier2012-11-261-1/+0
| | | | | | | | | | | | | | | This pass was conservative in that it always reserved the FP to enable dynamic stack realignment, which allowed the RA to use aligned spills for vector registers. This happens even when spills were not necessary. The RA has since been improved to use unaligned spills when necessary. The new behavior is to realign the stack if the frame pointer was already reserved for some other reason, but don't reserve the frame pointer just because a function contains vector virtual registers. Part of rdar://12719844 llvm-svn: 168627
* Remove TargetELFWriterInfo.Rafael Espindola2012-10-281-1/+0
| | | | | | All the credit goes to Jan Voung for noticing it was dead! llvm-svn: 166902
* Implement a basic VectorTargetTransformInfo interface to be used by the loop ↵Nadav Rotem2012-10-241-2/+2
| | | | | | and bb vectorizers for modeling the cost of instructions. llvm-svn: 166593
* Reapply the TargerTransformInfo changes, minus the changes to LSR and ↵Nadav Rotem2012-10-181-2/+4
| | | | | | Lowerinvoke. llvm-svn: 166248
* Temporarily revert the TargetTransform changes.Bob Wilson2012-10-181-4/+2
| | | | | | | | | | | The TargetTransform changes are breaking LTO bootstraps of clang. I am working with Nadav to figure out the problem, but I am reverting it for now to get our buildbots working. This reverts svn commits: 165665 165669 165670 165786 165787 165997 and I have also reverted clang svn 165741 llvm-svn: 166168
* Add a new interface to allow IR-level passes to access codegen-specific ↵Nadav Rotem2012-10-101-2/+4
| | | | | | information. llvm-svn: 165665
* Move TargetData to DataLayout.Micah Villmow2012-10-081-2/+2
| | | | llvm-svn: 165402
* The early if conversion pass is ready to be used as an opt-in.Jakob Stoklund Olesen2012-10-031-1/+7
| | | | | | | | | | | Enable the pass by default for targets that request it, and change the -enable-early-ifcvt to the opposite -disable-early-ifcvt. There are still some x86 regressions when enabling early if-conversion because of the missing machine models. Disable the pass for x86 until machine models are added. llvm-svn: 165075
* Add early if-conversion support to X86.Jakob Stoklund Olesen2012-07-041-1/+6
| | | | | | | | | Implement the TII hooks needed by EarlyIfConversion to create cmov instructions and estimate their latency. Early if-conversion is still not enabled by default. llvm-svn: 159695
* Add all codegen passes to the PassManager via TargetPassConfig.Bob Wilson2012-07-021-7/+7
| | | | | | | | This is a preliminary step toward having TargetPassConfig be able to start and stop the compilation at specified passes for unit testing and debugging. No functionality change. llvm-svn: 159567
* Implement the local-dynamic TLS model for x86 (PR3985)Hans Wennborg2012-06-011-0/+4
| | | | | | | | | This implements codegen support for accesses to thread-local variables using the local-dynamic model, and adds a clean-up pass so that the base address for the TLS block can be re-used between local-dynamic access on an execution path. llvm-svn: 157818
* Change the PassManager from a reference to a pointer.Bill Wendling2012-05-011-6/+6
| | | | | | | | | The TargetPassManager's default constructor wants to initialize the PassManager to 'null'. But it's illegal to bind a null reference to a null l-value. Make the ivar a pointer instead. PR12468 llvm-svn: 155902
* TargetPassConfig: confine the MC configuration to TargetMachine.Andrew Trick2012-02-041-6/+4
| | | | | | | | | | Passes prior to instructon selection are now split into separate configurable stages. Header dependencies are simplified. The bulk of this diff is simply removal of the silly DisableVerify flags. Sorry for the target header churn. Attempting to stabilize them. llvm-svn: 149754
* Added TargetPassConfig. The first little step toward configuring codegen passes.Andrew Trick2012-02-031-8/+36
| | | | | | | | | | | Allows command line overrides to be centralized in LLVMTargetMachine.cpp. LLVMTargetMachine can intercept common passes and give precedence to command line overrides. Allows adding "internal" target configuration options without touching TargetOptions. Encapsulates the PassManager. Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs. Allows modifying the target configuration hooks without rebuilding the world. llvm-svn: 149672
* whitespaceAndrew Trick2012-02-031-1/+1
| | | | llvm-svn: 149671
* Instruction scheduling itinerary for Intel Atom.Andrew Trick2012-02-011-1/+2
| | | | | | | | | | | | | | Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
* Support segmented stacks on mac.Rafael Espindola2012-01-111-3/+0
| | | | | | | | This uses TLS slot 90, which actually belongs to JavaScriptCore. We only support frames with static size Patch by Brian Anderson. llvm-svn: 147960
* Remove hasXMM/hasXMMInt functions. Move callers to hasSSE1/hasSSE2. This is ↵Craig Topper2012-01-101-1/+1
| | | | | | the final piece to remove the AVX hack that disabled SSE. llvm-svn: 147843
* Unweaken vtables as per ↵David Blaikie2011-12-201-0/+2
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-6/+12
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* Turn on vzeroupper insertion on call boundaries for AVX; it works as far as ↵Eli Friedman2011-11-171-1/+1
| | | | | | I know, and I'd like to see wider testing. llvm-svn: 144867
* Sink codegen optimization level into MCCodeGenInfo along side relocation modelEvan Cheng2011-11-161-16/+14
| | | | | | | and code model. This eliminates the need to pass OptLevel flag all over the place and makes it possible for any codegen pass to use this information. llvm-svn: 144788
* Remove code to enable execution dependency fix pass on VR256. VR128 is ↵Craig Topper2011-11-161-9/+3
| | | | | | sufficient after r144636. llvm-svn: 144777
* Properly qualify AVX2 specific parts of execution dependency table. Also ↵Craig Topper2011-11-151-4/+1
| | | | | | enable converting between 256-bit PS/PD operations when AVX1 is enabled. Fixes PR11370. llvm-svn: 144622
* Enable execution dependency fix pass for YMM registers when AVX2 is enabled. ↵Craig Topper2011-11-091-4/+12
| | | | | | Add AVX2 logical operations to list of replaceable instructions. llvm-svn: 144179
* Revert "Turn on the vzeroupper pass by default."Eric Christopher2011-10-181-1/+1
| | | | | | This reverts commit 494f7ac3e8d2ab3d94e52317abf9c42a949fe1f3. llvm-svn: 142455
* Turn on the vzeroupper pass by default.Eric Christopher2011-10-181-1/+1
| | | | | | I'll remove/rename the option in a few days. llvm-svn: 142439
* A few 80-col violations.Evan Cheng2011-10-141-4/+8
| | | | llvm-svn: 141988
* Fixed natural stack alignment for Linux x86-32. Thanks Eli.Lang Hames2011-10-111-1/+1
| | | | llvm-svn: 141616
* Add a natural stack alignment field to TargetData, and prevent InstCombine fromLang Hames2011-10-101-4/+4
| | | | | | | | | | | | | | promoting allocas to preferred alignments that exceed the natural alignment. This avoids some potentially expensive dynamic stack realignments. The natural stack alignment is set in target data strings via the "S<size>" option. Size is in bits and must be a multiple of 8. The natural stack alignment defaults to "unspecified" (represented by a zero value), and the "unspecified" value does not prevent any alignment promotions. Target maintainers that care about avoiding promotions should explicitly add the "S<size>" option to their target data strings. llvm-svn: 141599
* Remove X86-dependent stuff from SSEDomainFix.Jakob Stoklund Olesen2011-09-271-1/+1
| | | | | | | | | This also enables domain swizzling for AVX code which required a few trivial test changes. The pass will be moved to lib/CodeGen shortly. llvm-svn: 140659
* Enable SSEDomainFix pass for AVX mode.Bruno Cardoso Lopes2011-09-151-4/+7
| | | | llvm-svn: 139816
* Use internal storage for command line option.Benjamin Kramer2011-09-031-5/+3
| | | | llvm-svn: 139079
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Introduce a pass to insert vzeroupper instructions to avoid AVX toBruno Cardoso Lopes2011-08-231-0/+16
| | | | | | | | | | SSE transition penalty. The pass is enabled through the "x86-use-vzeroupper" llc command line option. This is only the first step (very naive and conservative one) to sketch out the idea, but proper DFA is coming next to allow smarter decisions. Comments and ideas now and in further commits will be very appreciated. llvm-svn: 138317
* More refactoring.Evan Cheng2011-07-251-37/+0
| | | | llvm-svn: 135939
* - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.Evan Cheng2011-07-201-26/+7
| | | | | | | | - Introduce JITDefault code model. This tells targets to set different default code model for JIT. This eliminates the ugly hack in TargetMachine where code model is changed after construction. llvm-svn: 135580
* Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng2011-07-191-64/+12
| | | | | | | (including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. llvm-svn: 135468
* Rename createAsmInfo to createMCAsmInfo and move registration code to ↵Evan Cheng2011-07-141-21/+0
| | | | | | MCTargetDesc to prepare for next round of changes. llvm-svn: 135219
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-2/+2
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Restore old behavior. Always auto-detect features unless cpu or features are ↵Evan Cheng2011-07-081-1/+1
| | | | | | specified. llvm-svn: 134757
* Eliminate asm parser's dependency on TargetMachine:Evan Cheng2011-07-081-1/+1
| | | | | | | | | | - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". llvm-svn: 134678
* Add Mode64Bit feature and sink it down to MC layer.Evan Cheng2011-07-071-1/+1
| | | | llvm-svn: 134641
* Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-301-3/+6
| | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! llvm-svn: 134127
* Rename TargetOptions::StackAlignment to StackAlignmentOverride.Evan Cheng2011-06-231-1/+1
| | | | llvm-svn: 133739
* Remove TargetOptions.h dependency from X86Subtarget.Evan Cheng2011-06-231-1/+5
| | | | llvm-svn: 133726
* Add a getExprForPersonalitySymbol method to MCAsmInfo. Use it whenRafael Espindola2011-04-281-2/+6
| | | | | | converting the symbol passed to .cfi_personality into bytes is the file. llvm-svn: 130400
* ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows()Daniel Dunbar2011-04-191-24/+14
| | | | | | predicates. llvm-svn: 129816
* Add datalayout information for the IEEE quad precision fp128 type.Duncan Sands2011-03-011-4/+4
| | | | llvm-svn: 126780
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