| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 138660
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registeration and creation code into XXXMCDesc libraries.
llvm-svn: 135184
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and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
MCSubtargetInfo so MC code emitter can do the right thing.
llvm-svn: 134884
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unknown x86/non-x86 targets.
llvm-svn: 134773
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cmov for 64-bit targets.
llvm-svn: 134768
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specified.
llvm-svn: 134757
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Clean up all the other hacks which are now unnecessary.
llvm-svn: 134753
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llvm-svn: 134741
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- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
to generate asm matcher subtarget feature queries. e.g.
"ModeThumb,FeatureThumb2" is translated to
"(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
llvm-svn: 134678
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llvm-svn: 134641
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llvm-svn: 134606
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llvm-svn: 134281
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llvm-svn: 134259
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itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
and hide more details from targets.
llvm-svn: 134257
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be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.
The fix is to just have the clients explictly pass the CPU name!
llvm-svn: 134127
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llvm-svn: 133726
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llvm-svn: 131476
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triple component.
llvm-svn: 129838
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llvm-svn: 129813
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llvm-svn: 126226
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llvm-svn: 126130
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16 bytes for PR8969. Update all testcases accordingly.
llvm-svn: 123367
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llvm-svn: 121677
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the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable.
llvm-svn: 121439
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llvm-svn: 120923
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llvm-svn: 120298
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defaults to small pic code model.
llvm-svn: 111741
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llvm-svn: 109206
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llvm-svn: 107625
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symbols as declarations in the X86 backend. This would manifest
on darwin x86-32 as errors like this with -fvisibility=hidden:
symbol '__ZNSbIcED1Ev' can not be undefined in a subtraction expression
This fixes PR7353.
llvm-svn: 105954
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To support this, move IsCalleePop from X86ISelLowering to X86Subtarget.
llvm-svn: 104866
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llvm-svn: 102493
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llvm-svn: 101979
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a new subtarget option for AES and check for the support. Add "westmere"
line of processors and add AES-NI support to the core i7.
Add a couple of TODOs for information I couldn't verify.
llvm-svn: 100231
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llvm-svn: 100089
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llvm-svn: 98810
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fix the rest of the buildbot failures on non-x86 hosts.
llvm-svn: 98522
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Modules and ModuleProviders. Because the "ModuleProvider" simply materializes
GlobalValues now, and doesn't provide modules, it's renamed to
"GVMaterializer". Code that used to need a ModuleProvider to materialize
Functions can now materialize the Functions directly. Functions no longer use a
magic linkage to record that they're materializable; they simply ask the
GVMaterializer.
Because the C ABI must never change, we can't remove LLVMModuleProviderRef or
the functions that refer to it. Instead, because Module now exposes the same
functionality ModuleProvider used to, we store a Module* in any
LLVMModuleProviderRef and translate in the wrapper methods. The bindings to
other languages still use the ModuleProvider concept. It would probably be
worth some time to update them to follow the C++ more closely, but I don't
intend to do it.
Fixes http://llvm.org/PR5737 and http://llvm.org/PR5735.
llvm-svn: 94686
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ignore alignment requirements for SIMD memory operands. This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.
llvm-svn: 93151
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llvm-svn: 92648
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partial update instructions unless optimizing for size.
llvm-svn: 91910
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be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.
movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0
instead of
cvtss2sd (%rdi), %xmm0
An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0
llvm-svn: 91672
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current form, it is too expensive in compile time.
llvm-svn: 90781
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and support for blockaddresses in x86-32 PIC mode.
llvm-svn: 89506
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- This is an initial step towards -march=native support in Clang, and towards
eliminating host dependencies in the targets. See PR5389.
- Patch by Roman Divacky!
llvm-svn: 88768
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along the critical path.
llvm-svn: 88682
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llvm-svn: 86634
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llvm-svn: 84200
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non-pic mode. rdar://7187172.
llvm-svn: 80904
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llvm-svn: 80892
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