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* Trivial change to set UseLeaForSP flag in addition to togglingPreston Gurd2012-04-261-0/+2
| | | | | | | | the FeatureLeaForSP feature bit when llvm auto detects Intel Atom. Patch by Andy Zhang llvm-svn: 155655
* Enable detection of AVX and AVX2 support through CPUID. Add AVX/AVX2 to ↵Craig Topper2012-04-261-7/+5
| | | | | | corei7-avx, core-avx-i, and core-avx2 cpu names. llvm-svn: 155618
* This patch fixes a problem which arose when using the Post-RA schedulerPreston Gurd2012-04-231-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on X86 Atom. Some of our tests failed because the tail merging part of the BranchFolding pass was creating new basic blocks which did not contain live-in information. When the anti-dependency code in the Post-RA scheduler ran, it would sometimes rename the register containing the function return value because the fact that the return value was live-in to the subsequent block had been lost. To fix this, it is necessary to run the RegisterScavenging code in the BranchFolding pass. This patch makes sure that the register scavenging code is invoked in the X86 subtarget only when post-RA scheduling is being done. Post RA scheduling in the X86 subtarget is only done for Atom. This patch adds a new function to the TargetRegisterClass to control whether or not live-ins should be preserved during branch folding. This is necessary in order for the anti-dependency optimizations done during the PostRASchedulerList pass to work properly when doing Post-RA scheduling for the X86 in general and for the Intel Atom in particular. The patch adds and invokes the new function trackLivenessAfterRegAlloc() instead of using the existing requiresRegisterScavenging(). It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of requiresRegisterScavenging(). It changes the all the targets that implemented requiresRegisterScavenging() to also implement trackLivenessAfterRegAlloc(). It adds an assertion in the Post RA scheduler to make sure that post RA liveness information is available when it is needed. It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order to avoid running into the added assertion. Finally, this patch restores the use of anti-dependency checking (which was turned off temporarily for the 3.1 release) for Intel Atom in the Post RA scheduler. Patch by Andy Zhang! Thanks to Jakob and Anton for their reviews. llvm-svn: 155395
* Temporarily turn off anti-dependency checkingPreston Gurd2012-04-161-1/+3
| | | | | | | | during Post RA scheduling in X86, until the X86 target is changed to properly set up post RA liveness. llvm-svn: 154874
* Prune some includesCraig Topper2012-03-271-1/+0
| | | | llvm-svn: 153502
* Remove extra semi-colons.Chad Rosier2012-02-221-1/+1
| | | | llvm-svn: 151169
* Use LEA to adjust stack ptr for Atom. Patch by Andy Zhang.Evan Cheng2012-02-071-0/+2
| | | | llvm-svn: 150008
* Instruction scheduling itinerary for Intel Atom.Andrew Trick2012-02-011-1/+30
| | | | | | | | | | | | | | Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
* PR11834: Use macros which are defined on Windows. Patch by Marina Yatsina.Evan Cheng2012-01-301-1/+2
| | | | llvm-svn: 149294
* Default stack alignment for 32bit x86 should be 4 Bytes, not 8 Bytes.Joerg Sonnenberger2012-01-101-1/+1
| | | | | | | Add a test that checks the stack alignment of a simple function for Darwin, Linux and NetBSD for 32bit and 64bit mode. llvm-svn: 147888
* Remove AVX hack in X86Subtarget. AVX/AVX2 are now treated as an SSE level. ↵Craig Topper2012-01-091-8/+3
| | | | | | Predicate functions have been altered to maintain previous names and behavior. llvm-svn: 147770
* Don't disable MMX support when AVX is enabled. Fix predicates for MMX ↵Craig Topper2012-01-091-1/+1
| | | | | | instructions that were added along with SSE instructions to check for AVX in addition to SSE level. llvm-svn: 147762
* Change XOP detection to use the correct CPUID bit instead of using the FMA4 bit.Craig Topper2011-12-291-9/+13
| | | | llvm-svn: 147348
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-3/+0
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* Add XOP feature flag.Jan Sjödin2011-12-021-0/+3
| | | | llvm-svn: 145682
* Add intrinsics and feature flag for read/write FS/GS base instructions. Also ↵Craig Topper2011-10-301-0/+11
| | | | | | add AVX2 feature flag. llvm-svn: 143319
* Remove NaClModeDavid Meyer2011-10-181-7/+1
| | | | llvm-svn: 142338
* Don't use inline assembly in 64-bit Visual Studio. Unfortunately, this means ↵Craig Topper2011-10-171-8/+9
| | | | | | that cpuid leaf 7 can't be queried on versions of Visual Studio earlier than VS 2008 SP1. Fixes PR11147. llvm-svn: 142177
* Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper2011-10-161-0/+5
| | | | llvm-svn: 142122
* Add X86 feature detection support for BMI instructions. Added new cpuid ↵Craig Topper2011-10-161-18/+34
| | | | | | function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7. llvm-svn: 142089
* Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 ↵Craig Topper2011-10-141-0/+1
| | | | | | processor which is gcc's name for Haswell. llvm-svn: 141939
* Add X86 LZCNT instruction. Including instruction selection support.Craig Topper2011-10-111-0/+5
| | | | llvm-svn: 141651
* Put a bunch of calls to ToggleFeature behind proper if statements.Craig Topper2011-10-101-17/+42
| | | | llvm-svn: 141527
* Add Ivy Bridge 16-bit floating point conversion instructions for the X86 ↵Craig Topper2011-10-091-0/+2
| | | | | | disassembler. llvm-svn: 141505
* Add support for MOVBE and RDRAND instructions for the assembler and ↵Craig Topper2011-10-031-0/+4
| | | | | | disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. llvm-svn: 141007
* Detect attempt to use segmented stacks on non ELF systems and errorRafael Espindola2011-09-071-0/+5
| | | | | | (not assert) early. llvm-svn: 139233
* Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certainNick Lewycky2011-09-051-1/+7
| | | | | | | instructions are more aligned than the CPU requires, and adds some additional directives, to follow in future patches. Patch by David Meyer! llvm-svn: 139125
* Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.Eli Friedman2011-08-261-0/+2
| | | | llvm-svn: 138660
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-2/+0
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-24/+46
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Really force on 64bit for 64-bit targets. Should fix remaining failures on ↵Eli Friedman2011-07-081-3/+11
| | | | | | unknown x86/non-x86 targets. llvm-svn: 134773
* Revert earlier unnecessary hack. Make sure we correctly force on 64bit and ↵Eli Friedman2011-07-081-3/+8
| | | | | | cmov for 64-bit targets. llvm-svn: 134768
* Restore old behavior. Always auto-detect features unless cpu or features are ↵Evan Cheng2011-07-081-18/+5
| | | | | | specified. llvm-svn: 134757
* Default 64-bit target features and SSE2 on when a triple specifies x86-64. ↵Eli Friedman2011-07-081-10/+0
| | | | | | Clean up all the other hacks which are now unnecessary. llvm-svn: 134753
* For non-x86 host, used generic as CPU name.Evan Cheng2011-07-081-5/+10
| | | | llvm-svn: 134741
* Eliminate asm parser's dependency on TargetMachine:Evan Cheng2011-07-081-1/+2
| | | | | | | | | | - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". llvm-svn: 134678
* Add Mode64Bit feature and sink it down to MC layer.Evan Cheng2011-07-071-83/+32
| | | | llvm-svn: 134641
* Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng2011-07-071-2/+2
| | | | llvm-svn: 134606
* Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.Evan Cheng2011-07-011-1/+1
| | | | llvm-svn: 134281
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-011-1/+1
| | | | llvm-svn: 134259
* - Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng2011-07-011-2/+8
| | | | | | | | | itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. llvm-svn: 134257
* Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-301-4/+7
| | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! llvm-svn: 134127
* Remove TargetOptions.h dependency from X86Subtarget.Evan Cheng2011-06-231-34/+5
| | | | llvm-svn: 133726
* Enable autodetect of popcntMon P Wang2011-05-171-0/+1
| | | | llvm-svn: 131476
* ADT/Triple: Renambe isOSX... methods to isMacOSX for consistency with the OSDaniel Dunbar2011-04-201-1/+2
| | | | | | triple component. llvm-svn: 129838
* Target/X86: Eliminate uses of getDarwinVers().Daniel Dunbar2011-04-191-1/+1
| | | | llvm-svn: 129813
* Stack alignment is 16 bytes on FreeBSD/i386 too.Roman Divacky2011-02-221-3/+4
| | | | llvm-svn: 126226
* The stack should be 16 byte aligned on 32 bit solaris. Patch by Yuri.Duncan Sands2011-02-211-3/+3
| | | | llvm-svn: 126130
* Experiment with changing the default 32-bit linux stack alignment toEric Christopher2011-01-131-3/+3
| | | | | | 16 bytes for PR8969. Update all testcases accordingly. llvm-svn: 123367
* Disable auto-detection of AVX support since AVX codegen support is not ready.Evan Cheng2010-12-131-1/+2
| | | | llvm-svn: 121677
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