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path: root/llvm/lib/Target/X86/X86Subtarget.cpp
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* Remove bunch of gcc 4.3-related warnings from TargetAnton Korobeynikov2008-02-201-1/+2
| | | | llvm-svn: 47369
* Remove warning about 64-bit code on processorDale Johannesen2008-02-151-6/+0
| | | | | | that doesn't support it. Per Chris. llvm-svn: 47162
* Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing ↵Evan Cheng2008-02-071-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mode. Before: _main: subq $8, %rsp leaq _X(%rip), %rax movsd 8(%rax), %xmm1 movss _X(%rip), %xmm0 call _t xorl %ecx, %ecx movl %ecx, %eax addq $8, %rsp ret Now: _main: subq $8, %rsp movsd _X+8(%rip), %xmm1 movss _X(%rip), %xmm0 call _t xorl %ecx, %ecx movl %ecx, %eax addq $8, %rsp ret Notice there is another idiotic codegen issue that needs to be fixed asap: xorl %ecx, %ecx movl %ecx, %eax llvm-svn: 46850
* SSE 4.1 Intrinsics and detectionNate Begeman2008-02-031-0/+2
| | | | llvm-svn: 46681
* Enable PIC codegen on x86-64/linuxAnton Korobeynikov2008-01-201-1/+1
| | | | llvm-svn: 46198
* Use size_t to store Pos, avoid truncating valueDuncan Sands2008-01-081-1/+1
| | | | | | | | on 64-bit builds. Analysis and original patch by Török Edwin. Code audit found another place with the same problem, also fixed here. llvm-svn: 45746
* darwin9 and above support aligned common symbols.Chris Lattner2008-01-021-10/+22
| | | | llvm-svn: 45494
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Make ARM an X86 memcpy expansion more similar to each other.Rafael Espindola2007-10-311-1/+1
| | | | | | | | Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it. This should not change generated code. llvm-svn: 43552
* Mac OS X X86-64 low 4G address not available.Evan Cheng2007-08-011-0/+4
| | | | llvm-svn: 40701
* Here is the bulk of the sanitizing.Gabor Greif2007-07-051-1/+1
| | | | | | Almost all occurrences of "bytecode" in the sources have been eliminated. llvm-svn: 37913
* In the event that some really old non-Intel or -AMD CPU is encountered...Jeff Cohen2007-04-161-2/+5
| | | | llvm-svn: 36177
* Before assuming that the original code didn't work for Athlon64, the person whoJeff Cohen2007-04-161-6/+2
| | | | | | | replaced it with a FIXME should have determined what did work. Then he would have realized that the code was in fact correct, and would have avoided breaking it. llvm-svn: 36173
* Add support for our first SSSE3 instruction "pmulhrsw".Bill Wendling2007-04-101-0/+1
| | | | llvm-svn: 35869
* Autodetect MMX & SSE stuff for AMD processorsAnton Korobeynikov2007-03-231-10/+11
| | | | llvm-svn: 35292
* For PR1136: Rename GlobalVariable::isExternal as isDeclaration to avoidReid Spencer2007-01-301-2/+2
| | | | | | confusion with external linkage types. llvm-svn: 33663
* Propagate changes from my local tree. This patch includes:Anton Korobeynikov2007-01-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | 1. New parameter attribute called 'inreg'. It has meaning "place this parameter in registers, if possible". This is some generalization of gcc's regparm(n) attribute. It's currently used only in X86-32 backend. 2. Completely rewritten CC handling/lowering code inside X86 backend. Merged stdcall + c CCs and fastcall + fast CC. 3. Dropped CSRET CC. We cannot add struct return variant for each target-specific CC (e.g. stdcall + csretcc and so on). 4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in on first attribute has meaning 'This is hidden pointer to structure return. Handle it gently'. 5. Fixed small bug in llvm-extract + add new feature to FunctionExtraction pass, which relinks all internal-linkaged callees from deleted function to external linkage. This will allow further linking everything together. NOTEs: 1. Documentation will be updated soon. 2. llvm-upgrade should be improved to translate csret => sret. Before this, there will be some unexpected test fails. llvm-svn: 33597
* Linux GOT indirect reference is only necessary in PIC mode.Evan Cheng2007-01-221-1/+1
| | | | llvm-svn: 33441
* * Fix one more bug in PIC codegen: extra load is needed for *all*Anton Korobeynikov2007-01-171-1/+5
| | | | | | | | | non-statics. * Introduce new option to output zero-initialized data to .bss section. This can reduce size of binaries. Enable it by default for ELF & Cygwin/Mingw targets. Probably, Darwin should be also added. llvm-svn: 33299
* * PIC codegen for X86/Linux has been implementedAnton Korobeynikov2007-01-121-7/+8
| | | | | | | | * PIC-aware internal structures in X86 Codegen have been refactored * Visibility (default/weak) has been added * Docs fixes (external weak linkage, visibility, formatting) llvm-svn: 33136
* Really big cleanup.Anton Korobeynikov2007-01-031-4/+8
| | | | | | | | | | | - New target type "mingw" was introduced - Same things for both mingw & cygwin are marked as "cygming" (as in gcc) - .lcomm is supported here, so allow LLVM to use it - Correctly use underscored versions of setjmp & _longjmp for both mingw & cygwin llvm-svn: 32833
* Refactored JIT codegen for mingw32. Now we're using standart relocationAnton Korobeynikov2006-12-221-12/+3
| | | | | | type for distinguish JIT & non-JIT instead of "dirty" hacks :) llvm-svn: 32745
* Fixed 80 cols & style violationAnton Korobeynikov2006-12-201-2/+4
| | | | llvm-svn: 32720
* Fixed dllimported symbols support during JIT'ing. JIT on mingw32Anton Korobeynikov2006-12-201-7/+18
| | | | | | | platform should be more or less workable. At least, sim is running fine under lli :) llvm-svn: 32711
* What should be the last unnecessary <iostream>s in the library.Bill Wendling2006-12-071-4/+3
| | | | llvm-svn: 32333
* Factor out GVRequiresExtraLoad() from .h to .cppAnton Korobeynikov2006-11-301-0/+17
| | | | llvm-svn: 32048
* 16-byte stack alignment for X86-64 ELF. Patch by Dan Gohman.Evan Cheng2006-11-291-1/+3
| | | | llvm-svn: 32004
* Fix codegen for x86-64 on systems (like ppc or i386) that don't have 64-bitChris Lattner2006-11-201-8/+17
| | | | | | | features autodetected. This fixes PR1010 and Regression/CodeGen/X86/xmm-r64.ll on non-x86-64 hosts. llvm-svn: 31879
* Use movl+xchgl instead of pushl+popl.Evan Cheng2006-11-081-3/+2
| | | | llvm-svn: 31572
* Proper fix.Evan Cheng2006-10-171-5/+4
| | | | llvm-svn: 30993
* Proper fix for rdar://problem/4770604 Thanks to Stuart Hastings!Evan Cheng2006-10-161-12/+13
| | | | llvm-svn: 30985
* 80 col violation.Evan Cheng2006-10-061-3/+4
| | | | llvm-svn: 30770
* Still need to support -mcpu=<> or cross compilation will fail. Doh.Evan Cheng2006-10-061-3/+104
| | | | llvm-svn: 30764
* Do away with CPU feature list. Just use CPUID to detect MMX, SSE, SSE2, ↵Evan Cheng2006-10-061-90/+15
| | | | | | SSE3, and 64-bit support. llvm-svn: 30763
* It appears the inline asm in GetCpuIDAndInfo() may clobbers some registers ↵Evan Cheng2006-10-061-3/+3
| | | | | | if it isn't inlined (at < -O3). Force it to be inlined. llvm-svn: 30762
* Formating.Evan Cheng2006-10-041-1/+1
| | | | llvm-svn: 30722
* Committing X86-64 support.Evan Cheng2006-09-081-15/+32
| | | | llvm-svn: 30177
* Fix a cross-build issue. The asmsyntax shouldn't be affected by the buildChris Lattner2006-09-071-8/+12
| | | | | | | host, it should be affected by the target. Allow the command line option to override in either case. llvm-svn: 30164
* Make the x86 asm flavor part of the subtarget info.Jim Laskey2006-09-071-0/+16
| | | | llvm-svn: 30146
* Later models likely to have Yonah like attributes.Evan Cheng2006-06-161-1/+2
| | | | llvm-svn: 28843
* X86 / Cygwin asm / alignment fixes.Evan Cheng2006-05-251-1/+1
| | | | | | Patch contributed by Anton Korobeynikov! llvm-svn: 28480
* x86 / Darwin PIC support.Evan Cheng2006-02-181-4/+1
| | | | llvm-svn: 26273
* A bit more memset / memcpy optimization.Evan Cheng2006-02-161-0/+2
| | | | | | | Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned, 2) size is not known to be greater or equal to some minimum value (currently 128). llvm-svn: 26224
* DuhEvan Cheng2006-02-141-3/+0
| | | | llvm-svn: 26180
* Remove -disable-x86-sseEvan Cheng2006-02-141-10/+2
| | | | llvm-svn: 26179
* Enable SSE (for the right subtargets)Evan Cheng2006-02-141-6/+3
| | | | llvm-svn: 26169
* Flesh out AMD family/models.Jeff Cohen2006-01-281-2/+27
| | | | llvm-svn: 25755
* Correctly determine CPU vendor.Jeff Cohen2006-01-281-11/+5
| | | | llvm-svn: 25754
* Use union instead of reinterpret_cast.Jeff Cohen2006-01-281-5/+9
| | | | llvm-svn: 25751
* Fix recognition of Intel CPUs.Jeff Cohen2006-01-281-0/+2
| | | | llvm-svn: 25750
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