summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/X86/X86Subtarget.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* Delete X86JITInfo in the subtarget destructor.Eric Christopher2014-06-101-0/+1
| | | | llvm-svn: 210516
* Move all of the x86 subtarget initialized variables down into the x86 subtargetEric Christopher2014-06-091-2/+56
| | | | | | from the x86 target machine. Should be no functional change. llvm-svn: 210479
* [X86] Use ADD/SUB instead of INC/DEC for SilvermontAlexey Volkov2014-06-091-0/+1
| | | | | | | | | | | | According to Intel Software Optimization Manual on Silvermont INC or DEC instructions require an additional uop to merge the flags. As a result, a branch instruction depending on an INC or a DEC instruction incurs a 1 cycle penalty. Differential Revision: http://reviews.llvm.org/D3990 llvm-svn: 210466
* Fix compilation issues.Eric Christopher2014-05-211-2/+3
| | | | llvm-svn: 209342
* Make early if conversion dependent upon the subtarget and addEric Christopher2014-05-211-0/+12
| | | | | | | a subtarget hook to enable. Unconditionally add to the pass pipeline for targets that might want to use it. No functional change. llvm-svn: 209340
* [X86] Tune LEA usage for SilvermontAlexey Volkov2014-05-201-0/+1
| | | | | | | | | | | | | According to Intel Software Optimization Manual on Silvermont in some cases LEA is better to be replaced with ADD instructions: "The rule of thumb for ADDs and LEAs is that it is justified to use LEA with a valid index and/or displacement for non-destructive destination purposes (especially useful for stack offset cases), or to use a SCALE. Otherwise, ADD(s) are preferable." Differential Revision: http://reviews.llvm.org/D3826 llvm-svn: 209198
* Reformat a couple of functions for clarity.Eric Christopher2014-05-071-22/+19
| | | | llvm-svn: 208248
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-1/+1
| | | | llvm-svn: 207197
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-3/+4
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* [cleanup] Lift using directives, DEBUG_TYPE definitions, and even someChandler Carruth2014-04-221-4/+4
| | | | | | | | | | | | system headers above the includes of generated '.inc' files that actually contain code. In a few targets this was already done pretty consistently, but it wasn't done *really* consistently anywhere. It is strictly cleaner IMO and necessary in a bunch of places where the DEBUG_TYPE is referenced from the generated code. Consistency with the necessary places trumps. Hopefully the build bots are OK with the movement of intrin.h... llvm-svn: 206838
* X86: Remove TargetMachine CPU auto-detection.Jim Grosbach2014-04-121-281/+15
| | | | | | | | This logic is properly in the realm of whatever is creating the TargetMachine. This makes plain 'llc foo.ll' consistent across heterogenous machines. llvm-svn: 206094
* X86: Disable IsLegalToCallImmediateAddr for Win32David Majnemer2014-03-281-1/+4
| | | | | | | | | | WinCOFF cannot form PC relative relocations to support absolute MCValues. We should reenable this once WinCOFF supports emission of IMAGE_REL_I386_REL32 relocations. This fixes PR19272. llvm-svn: 205058
* [x86] Support i386-*-*-code16 triple for emitting 16-bit codeDavid Woodhouse2014-01-201-2/+4
| | | | llvm-svn: 199648
* Decouple dllexport/dllimport from linkageNico Rieck2014-01-141-1/+1
| | | | | | | | | | | | | | | | | | | Representing dllexport/dllimport as distinct linkage types prevents using these attributes on templates and inline functions. Instead of introducing further mixed linkage types to include linkonce and weak ODR, the old import/export linkage types are replaced with a new separate visibility-like specifier: define available_externally dllimport void @f() {} @Var = dllexport global i32 1, align 4 Linkage for dllexported globals and functions is now equal to their linkage without dllexport. Imported globals and functions must be either declarations with external linkage, or definitions with AvailableExternallyLinkage. llvm-svn: 199218
* Revert "Decouple dllexport/dllimport from linkage"Nico Rieck2014-01-141-1/+1
| | | | | | | | Revert this for now until I fix an issue in Clang with it. This reverts commit r199204. llvm-svn: 199207
* Decouple dllexport/dllimport from linkageNico Rieck2014-01-141-1/+1
| | | | | | | | | | | | | | | | | | | Representing dllexport/dllimport as distinct linkage types prevents using these attributes on templates and inline functions. Instead of introducing further mixed linkage types to include linkonce and weak ODR, the old import/export linkage types are replaced with a new separate visibility-like specifier: define available_externally dllimport void @f() {} @Var = dllexport global i32 1, align 4 Linkage for dllexported globals and functions is now equal to their linkage without dllexport. Imported globals and functions must be either declarations with external linkage, or definitions with AvailableExternallyLinkage. llvm-svn: 199204
* [x86] Kill gratuitous X86_{32,64}TargetMachine subclasses, use X86TargetMachineDavid Woodhouse2014-01-081-3/+3
| | | | llvm-svn: 198720
* [x86] Add basic support for .code16Craig Topper2014-01-061-1/+9
| | | | | | | | | | | This is not really expected to work right yet. Mostly because we will still emit the OpSize (0x66) prefix in all the wrong places, along with a number of other corner cases. Those will all be fixed in the subsequent commits. Patch from David Woodhouse. llvm-svn: 198584
* X86: enable AVX2 under Haswell native compilationTim Northover2013-11-251-1/+6
| | | | | | Patch by Adam Strzelecki llvm-svn: 195632
* SHLD/SHRD are VectorPath (microcode) instructions known to have poor latency ↵Ekaterina Romanova2013-11-211-0/+10
| | | | | | | | | | on certain architectures. While generating SHLD/SHRD instructions is acceptable when optimizing for size, optimizing for speed on these platforms should be implemented using alternative sequences of instructions composed of add, adc, shr, shl, or and lea which are directPath instructions. These alternative instructions not only have a lower latency but they also increase the decode bandwidth by allowing simultaneous decoding of a third directPath instruction. AMD's processors family K7, K8, K10, K12, K15 and K16 are known to have SHLD/SHRD instructions with very poor latency. Optimization guides for these processors recommend using an alternative sequence of instructions. For these AMD's processors, I disabled folding (or (x << c) | (y >> (64 - c))) when we are not optimizing for size. It might be beneficial to disable this folding for some of the Intel's processors. However, since I couldn't find specific recommendations regarding using SHLD/SHRD instructions on Intel's processors, I haven't disabled this peephole for Intel. llvm-svn: 195383
* Adding a feature flag to the llvm backend for x86 TBM instruction set.Yunzhong Gao2013-09-241-0/+5
| | | | | | | | | | Adding TBM feature to bdver2 processor; piledriver supports this instruction set according to the following document: http://developer.amd.com/wordpress/media/2012/10/New-Bulldozer-and-Piledriver-Instructions.pdf Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1692 llvm-svn: 191324
* Prevent extra calls to ToggleFeature for Feature64Bit and FeatureCMOV if ↵Craig Topper2013-09-181-2/+2
| | | | | | they've already been enabled. The extra call ends up clearing the bit in FeatureBits since its a 'toggle'. Can't prove that anything was broken because of this since I don't think the FeatureBits for these are used. llvm-svn: 190920
* Fix X86 subtarget to not overwrite the autodetected features by calling ↵Craig Topper2013-09-181-1/+1
| | | | | | InitMCProcessorInfo right after detecting them. Instead add a new function that only updates the scheduling model and call that. llvm-svn: 190919
* Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd2013-09-131-2/+6
| | | | | | | | | | | Implements Instruction scheduler latencies for Silvermont, using latencies from the Intel Silvermont Optimization Guide. Auto detects SLM. Turns on post RA scheduler when generating code for SLM. llvm-svn: 190717
* Move operator to end of previous line to match coding standards.Craig Topper2013-09-131-2/+2
| | | | llvm-svn: 190659
* Partial support for Intel SHA Extensions (sha1rnds4)Ben Langmuir2013-09-121-0/+5
| | | | | | | | | Add basic assembly/disassembly support for the first Intel SHA instruction 'sha1rnds4'. Also includes feature flag, and test cases. Support for the remaining instructions will follow in a separate patch. llvm-svn: 190611
* Rename mattr names for AVX-512 to from avx-512 -> avx512f, avx-512-pfi -> ↵Craig Topper2013-08-211-1/+1
| | | | | | av512pf, avx-512-cdi -> avx512cd, avx-512-eri->avx512er. This matches better with official docs and what gcc patches appearto be using. I didn't touch the has* functions or the feature flag names to avoid change the td and lowering file while commits are still happening. llvm-svn: 188859
* Fix formatting. No functional change.Craig Topper2013-08-201-1/+1
| | | | llvm-svn: 188746
* Add AVX-512 and related features to the CPUID detection code.Craig Topper2013-08-201-3/+19
| | | | llvm-svn: 188745
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-281-0/+3
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
* Re-enable AVX detection on x64 platforms.Michael Kuperstein2013-05-071-1/+2
| | | | llvm-svn: 181313
* Unbreaking the non-x86 build bots by protecting the AVX test code properly.Aaron Ballman2013-05-031-0/+4
| | | | llvm-svn: 180992
* Correctly testing for AVX support in x86 based off code from Hosts.cpp.Aaron Ballman2013-05-031-1/+18
| | | | llvm-svn: 180991
* This patch adds the X86FixupLEAs pass, which will reduce instructionPreston Gurd2013-04-251-0/+1
| | | | | | | | latency for certain models of the Intel Atom family, by converting instructions into their equivalent LEA instructions, when it is both useful and possible to do so. llvm-svn: 180573
* Formatting.Eric Christopher2013-04-021-2/+1
| | | | llvm-svn: 178589
* Add support of RDSEED defined in AVX2 extensionMichael Liao2013-03-281-0/+5
| | | | llvm-svn: 178314
* Add ADX CPUID detectionMichael Liao2013-03-281-0/+4
| | | | llvm-svn: 178299
* For the current Atom processor, the fastest way to handle a callPreston Gurd2013-03-271-0/+1
| | | | | | | | | | | | | indirect through a memory address is to load the memory address into a register and then call indirect through the register. This patch implements this improvement by modifying SelectionDAG to force a function address which is a memory reference to be loaded into a virtual register. Patch by Sriram Murali. llvm-svn: 178171
* Add HLE target featureMichael Liao2013-03-261-0/+5
| | | | llvm-svn: 178082
* Add PREFETCHW codegen supportMichael Liao2013-03-261-0/+5
| | | | | | - Add 'PRFCHW' feature defined in AVX2 ISA extension llvm-svn: 178040
* Revert r176166 because it broke one of the lit tests.Nadav Rotem2013-02-271-4/+4
| | | | llvm-svn: 176171
* std::string to StringRef.Nadav Rotem2013-02-271-4/+4
| | | | llvm-svn: 176166
* Reinitialize the ivars in the subtarget so that they can be reset with the ↵Bill Wendling2013-02-161-32/+38
| | | | | | new features. llvm-svn: 175336
* Temporary revert of 175320.Bill Wendling2013-02-151-39/+33
| | | | llvm-svn: 175322
* Reinitialize the ivars in the subtarget.Bill Wendling2013-02-151-33/+39
| | | | | | | When we're recalculating the feature set of the subtarget, we need to have the ivars in their initial state. llvm-svn: 175320
* Use the 'target-features' and 'target-cpu' attributes to reset the subtarget ↵Bill Wendling2013-02-151-40/+60
| | | | | | | | | | features. If two functions require different features (e.g., `-mno-sse' vs. `-msse') then we want to honor that, especially during LTO. We can do that by resetting the subtarget's features depending upon the 'target-feature' attribute. llvm-svn: 175314
* added basic support for Intel ADX instructionsKay Tiong Khoo2013-02-141-0/+1
| | | | | | -feature flag, instructions definitions, test cases llvm-svn: 175196
* Restrict sin/cos optimization to 64-bit only for now. 32-bit is a bit messy ↵Evan Cheng2013-01-301-1/+2
| | | | | | and less critical. llvm-svn: 173987
* Teach SDISel to combine fsin / fcos into a fsincos node if the followingEvan Cheng2013-01-291-0/+5
| | | | | | | | | | | | | | | | | | conditions are met: 1. They share the same operand and are in the same BB. 2. Both outputs are used. 3. The target has a native instruction that maps to ISD::FSINCOS node or the target provides a sincos library call. Implemented the generic optimization in sdisel and enabled it for Mac OSX. Also added an additional optimization for x86_64 Mac OSX by using an alternative entry point __sincos_stret which returns the two results in xmm0 / xmm1. rdar://13087969 PR13204 llvm-svn: 173755
* Pad Short Functions for Intel AtomPreston Gurd2013-01-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The current Intel Atom microarchitecture has a feature whereby when a function returns early then it is slightly faster to execute a sequence of NOP instructions to wait until the return address is ready, as opposed to simply stalling on the ret instruction until the return address is ready. When compiling for X86 Atom only, this patch will run a pass, called "X86PadShortFunction" which will add NOP instructions where less than four cycles elapse between function entry and return. It includes tests. This patch has been updated to address Nadav's review comments - Optimize only at >= O1 and don't do optimization if -Os is set - Stores MachineBasicBlock* instead of BBNum - Uses DenseMap instead of std::map - Fixes placement of braces Patch by Andy Zhang. llvm-svn: 171879
OpenPOWER on IntegriCloud