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path: root/llvm/lib/Target/X86/X86SchedSkylakeServer.td
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* [X86] Add MOVQI2PQIrm, MOVSDmr, and MOVSDrm to scheduler informationCraig Topper2017-12-101-0/+3
| | | | | | The VEX versions were present but not the legacy SSE versions. llvm-svn: 320294
* [X86] Add LEA64_32r to scheduler models for ↵Craig Topper2017-12-101-1/+1
| | | | | | Sandybridge,Haswell,Broadwell,Skylake llvm-svn: 320293
* [X86] Add IN16/OUT16 to scheduling information for Haswell,Broadwell,SkylakeCraig Topper2017-12-101-4/+4
| | | | | | Sandy Bridge is also missing it, but it has other issues. See PR35590. llvm-svn: 320292
* [X86] Fix scheduler models to support ADD32ri in addition to ADD32ri8. ↵Craig Topper2017-12-101-16/+16
| | | | | | Similar for all sizes of AND/OR/XOR/SUB/ADC/SBB/CMP. llvm-svn: 320291
* [X86] Rename some instructions so that 'b' is added as a suffix instead of ↵Craig Topper2017-12-101-4/+4
| | | | | | replacing an 'r' llvm-svn: 320290
* [X86] Add CMPSDrr/rm to the scheduler models.Craig Topper2017-12-101-0/+2
| | | | | | Somehow CMPSSrr/rm was there and the VEX version was there, but this was consistently missing. llvm-svn: 320289
* [X86] Rename the rb form of scalar ADD/SUB/MUL/DIV to include _Int since ↵Craig Topper2017-12-101-12/+12
| | | | | | they can only be selected by intrinsics. llvm-svn: 320283
* [X86] Correct the _Int part of more scheduler model instrexes. Put _b in the ↵Craig Topper2017-12-101-78/+78
| | | | | | correct order relative to _Int llvm-svn: 320282
* [X86] Fix bad regular expressions in the scheduler models. Question marks ↵Craig Topper2017-12-101-87/+84
| | | | | | | | | | should be outside of multicharacter parenthesized expressions If the question mark is inside the parentheses it only applies to the single character proceeding it. I had to make a few additional cleanups to fix some duplicate warnings that were exposed by fixing this. llvm-svn: 320279
* [X86] Make the _Int part of some instregex sheduler patterns optionalCraig Topper2017-12-101-8/+8
| | | | llvm-svn: 320278
* [X86][FMA] Tag all FMA/FMA4 instructions with WriteFMA schedule classSimon Pilgrim2017-11-271-1/+1
| | | | | | | | | | As mentioned on PR17367, many instructions are missing scheduling tags preventing us from setting 'CompleteModel = 1' for better instruction analysis. This patch deals with FMA/FMA4 which is one of the bigger offenders (along with AVX512 in general). Annoyingly all scheduler models need to define WriteFMA (now that its actually used), even for older targets without FMA/FMA4 support, but that is an existing problem shared by other schedule classes. Differential Revision: https://reviews.llvm.org/D40351 llvm-svn: 319016
* [X86][SKX] Adding scheduling info of non-intrinsic + commutable SKX opcodes.Gadi Haber2017-11-131-102/+102
| | | | | | | | | | | | | | Updated the scheduling information of the SKX subtarget in the file X86SchedSkylakeServer.td under lib/Target/X86 to: 1. add regular opcodes in addition to the suffixed "_Int" opcodes 2. add the (V)MAXCPD/MAXCPS/MAXCSD/MAXCSS/MINCPD/MINCPS/MINCSD/MINCSS instructions that are equivalent to their counterparts without the 'C' as they are part of a hack to make floating point min/max commutable under fast math. Reviewers: zvi, RKSimon, craig.topper Differential Revision: https://reviews.llvm.org/D39833 Change-Id: Ie13702a5ce1b1a08af91ca637a52b6962881e7d6 llvm-svn: 318024
* [X86][SKX] Adding the scheduling information for the SKX target.Gadi Haber2017-10-081-0/+6949
Adding the scheduling information for the SkylakeServer (SKX) target. This patch adds the instruction scheduling information for the SkylakeServer (SKX) architecture target by adding the file X86SchedSkylakeServer.td located under the X86 Target. We used the scheduling information retrieved from the Skylake architects in order to create the file. The scheduling information includes latency, number of micro-Ops and used ports by each SKL instruction. The patch continues the scheduling replacement and insertion effort started with the SNB target in r310792, the HSW target in r311879 and the SkylakeClient (SKL) target in rL313613. Please expect some performance fluctuations due to code alignment effects. Reviewers: zvi, RKSimon, craig.topper, chandlerc, aymanmu Differential Revision: https://reviews.llvm.org/D38443 Change-Id: I5c228fcc09e9e5a99b6116e62b356c4f9b971185 llvm-svn: 315175
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