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path: root/llvm/lib/Target/X86/X86RegisterInfo.h
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* Add target a target hook to get the register number used by the compact unwindBill Wendling2011-06-301-0/+4
| | | | | | | encoding for the registers it knows about. Return -1 if it can't handle that register. llvm-svn: 134202
* Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng2011-06-271-1/+3
| | | | | | into XXXGenRegisterInfo.inc. llvm-svn: 133922
* Get rid of one getStackAlignment(). RegisterInfo shouldn't need to know ↵Evan Cheng2011-06-231-6/+0
| | | | | | about stack alignment. llvm-svn: 133679
* Use the dwarf->llvm mapping to print register names in the cfiRafael Espindola2011-05-301-0/+1
| | | | | | | | directives. Fixes PR9826. llvm-svn: 132317
* Add a method to TargetRegisterInfo to get the register number that the Win64 EHCharles Davis2011-05-241-0/+3
| | | | | | | scheme uses internally. Implement it for x86 (the only architecture that LLVM supports for which this matters right now). llvm-svn: 131969
* Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on ↵Jakob Stoklund Olesen2011-04-261-0/+3
| | | | | | | | | | | | register class inflation. The hook will be used by the register allocator when recomputing register classes after removing constraints. Thumb1 code doesn't allow anything larger than tGPR, and x86 needs to ensure that the spill size doesn't change. llvm-svn: 130228
* Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.Cameron Zwarich2011-03-071-0/+3
| | | | llvm-svn: 127175
* Move more PEI-related hooks to TFIAnton Korobeynikov2010-11-271-3/+0
| | | | llvm-svn: 120229
* Move some more hooks to TargetFrameInfoAnton Korobeynikov2010-11-201-2/+0
| | | | llvm-svn: 119904
* Move getInitialFrameState() to TargetFrameInfoAnton Korobeynikov2010-11-181-1/+0
| | | | llvm-svn: 119754
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-181-4/+0
| | | | llvm-svn: 119740
* First step of huge frame-related refactoring: move emit{Prologue,Epilogue} ↵Anton Korobeynikov2010-11-151-5/+4
| | | | | | out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place llvm-svn: 119097
* Simplify eliminateFrameIndex() interface back down now that PEI doesn't needJim Grosbach2010-08-261-3/+2
| | | | | | to try to re-use scavenged frame index reference registers. rdar://8277890 llvm-svn: 112241
* Constify some arguments.Eric Christopher2010-07-201-2/+2
| | | | llvm-svn: 108812
* Remove unused function.Rafael Espindola2010-06-021-6/+0
| | | | llvm-svn: 105325
* Rename X86 subregister indices to something shorter.Jakob Stoklund Olesen2010-05-241-10/+0
| | | | | | Use the tablegen-produced enums. llvm-svn: 104493
* Now that DBG_LABEL is updated, we can finally make MachineMove Chris Lattner2010-03-141-1/+1
| | | | | | contain an MCSymbol instead of a label index. llvm-svn: 98482
* Change the Value argument to eliminateFrameIndex to a type-tagged value. ThisJim Grosbach2010-03-091-1/+1
| | | | | | | | | | is preparatory to having PEI's scavenged frame index value reuse logic properly distinguish types of frame values (e.g., whether the value is stack-pointer relative or frame-pointer relative). No functionality change. llvm-svn: 98086
* Implement XMM subregs.Dan Gohman2010-02-281-1/+2
| | | | | | | | | | | Extracting the low element of a vector is now done with EXTRACT_SUBREG, and the zero-extension performed by load movss is now modeled with SUBREG_TO_REG, and so on. Register-to-register movss and movsd are no longer considered copies; they are two-address instructions which insert a scalar into a vector. llvm-svn: 97354
* constify a method argument.Chris Lattner2010-01-261-1/+1
| | | | llvm-svn: 94612
* For aligned load/store instructions, it's only required to know whether aJim Grosbach2010-01-191-0/+2
| | | | | | | | | | | function can support dynamic stack realignment. That's a much easier question to answer at instruction selection stage than whether the function actually will have dynamic alignment prologue. This allows the removal of the stack alignment heuristic pass, and improves code quality for cases where the heuristic would result in dynamic alignment code being generated when it was not strictly necessary. llvm-svn: 93885
* Make the MachineFunction argument of getFrameRegister const.David Greene2009-11-121-1/+1
| | | | | | This also fixes a build error. llvm-svn: 87027
* Add register-reuse to frame-index register scavenging. When a target usesJim Grosbach2009-10-071-2/+3
| | | | | | | | | | | | | | | | | | | | a virtual register to eliminate a frame index, it can return that register and the constant stored there to PEI to track. When scavenging to allocate for those registers, PEI then tracks the last-used register and value, and if it is still available and matches the value for the next index, reuses the existing value rather and removes the re-materialization instructions. Fancier tracking and adjustment of scavenger allocations to keep more values live for longer is possible, but not yet implemented and would likely be better done via a different, less special-purpose, approach to the problem. eliminateFrameIndex() is modified so the target implementations can return the registers they wish to be tracked for reuse. ARM Thumb1 implements and utilizes the new mechanism. All other targets are simply modified to adjust for the changed eliminateFrameIndex() prototype. llvm-svn: 83467
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-2/+2
| | | | | | own struct type. llvm-svn: 78610
* Give getPointerRegClass() a "kind" value so that targets can Chris Lattner2009-07-291-1/+1
| | | | | | support multiple different pointer register classes. llvm-svn: 77501
* Enable cross register class coalescing.Evan Cheng2009-07-181-0/+7
| | | | llvm-svn: 76281
* Targets sometimes assign fixed stack object to spill certain callee-savedEvan Cheng2009-07-091-1/+3
| | | | | | | | | | registers based on dynamic conditions. For example, X86 EBP/RBP, when used as frame register has to be spilled in the first fixed object. It should inform PEI this so it doesn't get allocated another stack object. Also, it should not be spilled as other callee-saved registers but rather its spilling and restoring are being handled by emitPrologue and emitEpilogue. Avoid spilling it twice. llvm-svn: 75116
* Recommit r74952 with a bug fix:Bill Wendling2009-07-081-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DWARF requires frame moves be specified at specific times. If you have a prologue like this: __Z3fooi: Leh_func_begin1: LBB1_0: ## entry pushl %ebp Llabel1: movl %esp, %ebp Llabel2: pushl %esi Llabel3: subl $20, %esp call "L1$pb" "L1$pb": popl %esi The "pushl %ebp" needs a table entry specifying the offset. The "movl %esp, %ebp" makes %ebp the new stack frame register, so that needs to be specified in DWARF. And "pushl %esi" saves the callee-saved %esi register, which also needs to be specified in DWARF. Before, all of this logic was in one method. This didn't work too well, because as you can see there are multiple FDE line entries that need to be created. This fix creates the "MachineMove" objects directly when they're needed; instead of waiting until the end, and losing information. There is some ugliness where we generate code like this: LBB22_0: ## entry pushl %ebp Llabel280: movl %esp, %ebp Llabel281: Llabel284: pushl %ebp <---------- pushl %ebx pushl %edi pushl %esi Llabel282: subl $328, %esp Notice the extra "pushl %ebp". If we generate a "machine move" instruction in the FDE for that pushl, the linker may get very confused about what value %ebp should have when exitting the function. I.e., it'll give it the value %esp instead of the %ebp value from the first "pushl". Not to mention that, in this case, %ebp isn't modified in the function (that's a separate bug). I put a small hack in to get it to work. It might be the only solution, but should be revisited once the above case is fixed. llvm-svn: 75047
* --- Reverse-merging (from foreign repository) r74952 into '.':Bill Wendling2009-07-071-1/+3
| | | | | | | | | U lib/Target/X86/X86RegisterInfo.cpp U lib/Target/X86/X86RegisterInfo.h Temporarily revert. This was causing an infinite loop in the linker on Leopard. llvm-svn: 74970
* DWARF requires frame moves be specified at specific times. If you have aBill Wendling2009-07-071-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | prologue like this: __Z3fooi: Leh_func_begin1: LBB1_0: ## entry pushl %ebp Llabel1: movl %esp, %ebp Llabel2: pushl %esi Llabel3: subl $20, %esp call "L1$pb" "L1$pb": popl %esi The "pushl %ebp" needs a table entry specifying the offset. The "movl %esp, %ebp" makes %ebp the new stack frame register, so that needs to be specified in DWARF. And "pushl %esi" saves the callee-saved %esi register, which also needs to be specified in DWARF. Before, all of this logic was in one method. This didn't work too well, because as you can see there are multiple FDE line entries that need to be created. This fix creates the "MachineMove" objects directly when they're needed; instead of waiting until the end, and losing information. llvm-svn: 74952
* Implement x86 h-register extract support.Dan Gohman2009-04-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | - Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. llvm-svn: 68962
* Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.Evan Cheng2009-02-061-0/+4
| | | | llvm-svn: 63938
* Tidy up #includes, deleting a bunch of unnecessary #includes.Dan Gohman2009-01-051-2/+0
| | | | llvm-svn: 61715
* For now, don't split live intervals around x87 stack register barriers. ↵Evan Cheng2008-10-271-0/+4
| | | | | | FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them. llvm-svn: 58230
* Wrap MVT::ValueType in a struct to get type safetyDuncan Sands2008-06-061-1/+1
| | | | | | | | | | | | | | | | and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
* Eastimate required stack alignment early, so we can decide, whether we will ↵Anton Korobeynikov2008-04-231-0/+2
| | | | | | need frame pointer or not llvm-svn: 50161
* Provide convenient helpers for some operationsAnton Korobeynikov2008-04-231-0/+5
| | | | llvm-svn: 50153
* Infrastructure for getting the machine code size of a function and an ↵Nicolas Geoffray2008-04-161-1/+1
| | | | | | instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
* Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.Evan Cheng2008-03-311-3/+0
| | | | llvm-svn: 48995
* Add information about callee-saved registers on Win64Anton Korobeynikov2008-03-221-0/+4
| | | | llvm-svn: 48692
* Recommitting parts of r48130. These do not appear to cause the observed ↵Christopher Lamb2008-03-111-0/+9
| | | | | | failures. llvm-svn: 48223
* Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.Evan Cheng2008-03-101-9/+0
| | | | llvm-svn: 48167
* Allow insert_subreg into implicit, target-specific values. Christopher Lamb2008-03-101-0/+9
| | | | | | | Change insert/extract subreg instructions to be able to be used in TableGen patterns. Use the above features to reimplement an x86-64 pseudo instruction as a pattern. llvm-svn: 48130
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-2/+2
| | | | llvm-svn: 46930
* Avoid needlessly casting away const qualifiers.Dan Gohman2008-02-081-1/+1
| | | | llvm-svn: 46877
* Frame index can be negative.Evan Cheng2008-02-021-1/+1
| | | | llvm-svn: 46655
* Add x86 specific getFrameIndexOffset(). This fixes local variable debugging ↵Evan Cheng2008-01-311-0/+1
| | | | | | info. llvm-svn: 46598
* Provide correct DWARF register numbering for debug information emission on ↵Anton Korobeynikov2008-01-251-1/+1
| | | | | | | | x86-32/Darwin. This should fix bunch of issues. llvm-svn: 46337
* Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson2008-01-071-55/+0
| | | | | | Some day I'll get it all moved over... llvm-svn: 45672
* Move some more functionality from MRegisterInfo to TargetInstrInfo.Owen Anderson2008-01-041-9/+1
| | | | llvm-svn: 45603
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