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* Revert r227728 due to bad line endings.Michael Kuperstein2015-02-011-3/+2
| | | | llvm-svn: 227746
* [X86] Convert esp-relative movs of function arguments to pushes, step 2Michael Kuperstein2015-02-011-2/+3
| | | | | | | | | | | | This moves the transformation introduced in r223757 into a separate MI pass. This allows it to cover many more cases (not only cases where there must be a reserved call frame), and perform rudimentary call folding. It still doesn't have a heuristic, so it is enabled only for optsize/minsize, with stack alignment <= 8, where it ought to be a fairly clear win. Differential Revision: http://reviews.llvm.org/D6789 llvm-svn: 227728
* Use 32-bit ebp for NaCl64 in a limited case: llvm.frameaddress.Jan Wen Voung2014-12-051-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Follow up to [x32] "Use ebp/esp as frame and stack pointer": http://reviews.llvm.org/D4617 In that earlier patch, NaCl64 was made to always use rbp. That's needed for most cases because rbp should hold a full 64-bit address within the NaCl sandbox so that load/stores off of rbp don't require sandbox adjustment (zeroing the top 32-bits, then filling those by adding r15). However, llvm.frameaddress returns a pointer and pointers are 32-bit for NaCl64. In this case, use ebp instead, which will make the register copy type check. A similar mechanism may be needed for llvm.eh.return, but is not added in this change. Test Plan: test/CodeGen/X86/frameaddr.ll Reviewers: dschuff, nadav Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D6514 llvm-svn: 223510
* Fix a typo in a comment.Craig Topper2014-11-201-1/+1
| | | | llvm-svn: 222412
* Remove unnecessary getTarget call now that the subtarget is cachedEric Christopher2014-09-031-4/+2
| | | | | | on the machine function. llvm-svn: 217070
* [x32] Fix FrameIndex check in SelectLEA64_32AddrPavel Chupin2014-08-201-0/+6
| | | | | | | | | | | | | | | | | | Summary: Fixes http://llvm.org/bugs/show_bug.cgi?id=20016 reproducible on new lea-5.ll case. Also use RSP/RBP for x32 lea to save 1 byte used for 0x67 prefix in ESP/EBP case. Test Plan: lea tests modified to include x32/nacl and new test added Reviewers: nadav, dschuff, t.p.northover Subscribers: llvm-commits, zinovy.nis Differential Revision: http://reviews.llvm.org/D4929 llvm-svn: 216065
* [x32] Use ebp/esp as frame and stack pointerPavel Chupin2014-08-071-9/+7
| | | | | | | | | | | | | | | | | | | | | | | Summary: Since pointers are 32-bit on x32 we can use ebp and esp as frame and stack pointer. Some operations like PUSH/POP and CFI_INSTRUCTION still require 64-bit register, so using 64-bit MachineFramePtr where required. X86_64 NaCl uses 64-bit frame/stack pointers, however it's been found that both isTarget64BitLP64 and isTarget64BitILP32 are true for NaCl. Addressing this issue here as well by making isTarget64BitLP64 false. Also mark hasReservedSpillSlot unreachable on X86. See inlined comments. Test Plan: Add one new simple test and upgrade 2 existing with x32 target case. Reviewers: nadav, dschuff Subscribers: llvm-commits, zinovy.nis Differential Revision: http://reviews.llvm.org/D4617 llvm-svn: 215091
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-10/+5
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-6/+14
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* TargetRegisterInfo: Remove function that fell out of use years ago.Benjamin Kramer2014-07-091-15/+0
| | | | llvm-svn: 212636
* Move X86RegisterInfo away from using the TargetMachine and onlyEric Christopher2014-06-101-21/+18
| | | | | | using the subtarget. llvm-svn: 210595
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-1/+1
| | | | llvm-svn: 207197
* [cleanup] Lift using directives, DEBUG_TYPE definitions, and even someChandler Carruth2014-04-221-2/+2
| | | | | | | | | | | | system headers above the includes of generated '.inc' files that actually contain code. In a few targets this was already done pretty consistently, but it wasn't done *really* consistently anywhere. It is strictly cleaner IMO and necessary in a bunch of places where the DEBUG_TYPE is referenced from the generated code. Consistency with the necessary places trumps. Hopefully the build bots are OK with the movement of intrin.h... llvm-svn: 206838
* Make consistent use of MCPhysReg instead of uint16_t throughout the tree.Craig Topper2014-04-041-1/+1
| | | | llvm-svn: 205610
* Prune includes in X86 target.Craig Topper2014-03-191-1/+0
| | | | llvm-svn: 204216
* Replace ValueTypes.h with MachineValueType.h if possible.Patrik Hagglund2014-03-151-1/+1
| | | | | | | | | Utilize the previous move of MVT to a separate header for all trivial cases (that don't need any further restructuring). Reviewed By: Tim Northover llvm-svn: 204003
* x86: Add missing break to getCallPreservedMask()Duncan P. N. Exon Smith2014-03-141-0/+1
| | | | | | | | | | | | This change brings getCallPreservedMask()'s logic in line with getCalleeSavedRegs(). While this changes the control flow slightly, the change is not currently observable. is64Bit must be false to get to the accidental fallthrough, but the case that we fall into (coldcc) does nothing unless is64Bit is true. llvm-svn: 203943
* x86: NFC: Make getCallPreservedMask() more similar to getCalleeSavedRegs()Duncan P. N. Exon Smith2014-03-141-4/+6
| | | | | | | Changing order of checks in getCallPreservedMask() to match getCalleeSavedRegs() so that the logic is easier to compare. llvm-svn: 203939
* x86: getCalleeSavedRegs() would crash on 0 (so don't default to it)Duncan P. N. Exon Smith2014-03-141-0/+1
| | | | | | | The current logic assumes that MF is not 0. Assert that it isn't, and remove the default of 0 from the header. llvm-svn: 203934
* [Stackmaps] Move the target-independent frame index elimination for ↵Juergen Ributzka2014-02-211-0/+9
| | | | | | | | | | | | stackmaps and patchpoints into target-specific code. The lowering of the frame index for stackmaps and patchpoints requires some target-specific magic and should therefore be handled in the target-specific eliminateFrameIndex method. This is related to <rdar://problem/16106219> llvm-svn: 201904
* Add two new calling conventions for runtime callsJuergen Ributzka2014-01-171-0/+12
| | | | | | | | | | | | | | This patch adds two new target-independent calling conventions for runtime calls - PreserveMost and PreserveAll. The target-specific implementation for X86-64 is defined as following: - Arguments are passed as for the default C calling convention - The same applies for the return value(s) - PreserveMost preserves all GPRs - except R11 - PreserveAll preserves all GPRs and all XMMs/YMMs - except R11 Reviewed by Lang and Philip llvm-svn: 199508
* [anyregcc] Fix callee-save mask for anyregccJuergen Ributzka2014-01-111-20/+30
| | | | | | | Use separate callee-save masks for XMM and YMM registers for anyregcc on X86 and select the proper mask depending on the target cpu we compile for. llvm-svn: 198985
* [Stackmap] Only the AnyReg calling convention should preserve all registers.Juergen Ributzka2013-12-141-5/+3
| | | | llvm-svn: 197316
* Revert the backend fatal error from r196939Reid Kleckner2013-12-101-6/+0
| | | | | | | | | | | | | | The combination of inline asm, stack realignment, and dynamic allocas turns out to be too common to reject out of hand. ASan inserts empy inline asm fragments and uses aligned allocas. Compiling any trivial function containing a dynamic alloca with ASan is enough to trigger the check. XFAIL the test cases that would be miscompiled and add one that uses the relevant functionality. llvm-svn: 196986
* Reland "Fix miscompile of MS inline assembly with stack realignment"Reid Kleckner2013-12-101-12/+15
| | | | | | | | | | | This re-lands commit r196876, which was reverted in r196879. The tests have been fixed to pass on platforms with a stack alignment larger than 4. Update to clang side tests will land shortly. llvm-svn: 196939
* Revert "Fix miscompile of MS inline assembly with stack realignment"Reid Kleckner2013-12-101-15/+12
| | | | | | | This reverts commit r196876. Its tests failed on the bots, so I'll figure it out tomorrow. llvm-svn: 196879
* Fix miscompile of MS inline assembly with stack realignmentReid Kleckner2013-12-101-12/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For stack frames requiring realignment, three pointers may be needed: - ebp to address incoming arguments - esi (could be any callee-saved register) to address locals - esp to address outgoing arguments We would use esi unconditionally without verifying that it did not conflict with inline assembly. This change doesn't do the verification, it simply emits a fatal error on functions that use stack realignment, dynamic SP adjustments, and inline assembly. Because stack realignment is common on Windows, we also no longer assume that MS inline assembly clobbers esp. Instead, we analyze the inline instructions for implicit definitions and check if esp is there. If so, we require the use of a base pointer and consider it in the condition above. Mostly fixes PR16830, but we could try harder to find a non-conflicting base pointer. Reviewers: sunfish Differential Revision: http://llvm-reviews.chandlerc.com/D1317 llvm-svn: 196876
* The WebKit_JS CC preserves the same registers as the C CC.Juergen Ributzka2013-11-161-0/+1
| | | | llvm-svn: 194936
* [Stackmap] Add AnyReg calling convention support for patchpoint intrinsic.Juergen Ributzka2013-11-081-0/+6
| | | | | | | | | | | | | | The idea of the AnyReg Calling Convention is to provide the call arguments in registers, but not to force them to be placed in a paticular order into a specified set of registers. Instead it is up tp the register allocator to assign any register as it sees fit. The same applies to the return value (if applicable). Differential Revision: http://llvm-reviews.chandlerc.com/D2009 Reviewed by Andy llvm-svn: 194293
* Fix the ExecutionDepsFix pass to handle AVX instructions.Andrew Trick2013-10-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This pass is needed to break false dependencies. Without it, unlucky register assignment can result in wild (5x) swings in performance. This pass was trying to handle AVX but not getting it right. AVX doesn't have partial register defs, it has unused register reads in which the high bits of a source operand are copied into the unused bits of the dest. Fixing this requires conservative liveness analysis. This is awkard because the pass already has its own pseudo-liveness. However, proper liveness is expensive, and we would like to use a generic utility to compute it. The fix only invokes liveness on-demand. It is rare to detect a case that needs undef-read dependence breaking, but when it happens, it can be needed many times within a very large block. I think the existing heuristic which uses a register window of 16 is too conservative for loop-carried false dependencies. If the loop is a reduction. The out-of-order engine may be able to execute several loop iterations in parallel. However, I'll leave this tuning exercise for next time. llvm-svn: 192635
* Remove getEHExceptionRegister and getEHHandlerRegister.Rafael Espindola2013-10-071-8/+0
| | | | | | They haven't been used for a long time. Patch by MathOnNapkins. llvm-svn: 192099
* Use function attributes to indicate that we don't want to realign the stack.Bill Wendling2013-08-011-2/+3
| | | | | | | | Function attributes are the future! So just query whether we want to realign the stack directly from the function instead of through a random target options structure. llvm-svn: 187618
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-281-1/+0
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
* Take advantage of the register enums being in order to remove a couple ↵Craig Topper2013-07-261-18/+4
| | | | | | static tables. llvm-svn: 187182
* I'm starting to commit KNL backend. I'll push patches one-by-one. This patch ↵Elena Demikhovsky2013-07-241-0/+28
| | | | | | | | includes support for the extended register set XMM16-31, YMM16-31, ZMM0-31. The full ISA you can see here: http://software.intel.com/en-us/intel-isa-extensions llvm-svn: 187030
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-3/+2
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183571
* Don't assume the registers will be enumerated sequentially.Chad Rosier2013-05-291-2/+5
| | | | llvm-svn: 182879
* Simplify logic now that r182490 is in place. No functional change intended.Chad Rosier2013-05-221-8/+8
| | | | llvm-svn: 182531
* x86_64: designate most general purpose and SSE registers as callee save ↵Peter Collingbourne2013-02-221-21/+25
| | | | | | under coldcc llvm-svn: 175911
* Move the eliminateCallFramePseudoInstr method from TargetRegisterInfoEli Bendersky2013-02-211-101/+0
| | | | | | | | | | | | | | | to TargetFrameLowering, where it belongs. Incidentally, this allows us to delete some duplicated (and slightly different!) code in TRI. There are potentially other layering problems that can be cleaned up as a result, or in a similar manner. The refactoring was OK'd by Anton Korobeynikov on llvmdev. Note: this touches the target interfaces, so out-of-tree targets may be affected. llvm-svn: 175788
* getX86SubSuperRegister has a special mode with High=true for i64 whichEli Bendersky2013-02-211-17/+9
| | | | | | | | | | exists solely to enable it to call itself for i8 with some registers. The proposed patch simplifies the function somewhat to make the High bit only meaningful for the i8 mode, which makes sense. No functional difference (getX86SubSuperRegister is not getting called from anywhere outside with i64 and High=true). llvm-svn: 175762
* [ms-inline asm] Make the comment a bit more verbose.Chad Rosier2013-02-201-2/+6
| | | | llvm-svn: 175641
* [ms-inline asm] Force the use of a base pointer if the MachineFunction includesChad Rosier2013-02-191-2/+4
| | | | | | | | | | | | | MS-style inline assembly. This is a follow-on to r175334. Forcing a FP to be emitted doesn't ensure it will be used. Therefore, force the base pointer as well. We now treat MS inline assembly in the same way we treat functions with dynamic stack realignment and VLAs. This guarantees the BP will be used to reference parameters and locals. rdar://13218191 llvm-svn: 175576
* Make helpers static. Add missing include so LLVMInitializeObjCARCOpts gets C ↵Benjamin Kramer2013-02-151-1/+1
| | | | | | linkage. llvm-svn: 175264
* [PEI] Pass the frame index operand number to the eliminateFrameIndex function.Chad Rosier2013-01-311-15/+10
| | | | | | | Each target implementation was needlessly recomputing the index. Part of rdar://13076458 llvm-svn: 174083
* In this patch, we teach X86_64TargetMachine that it has a ILP32Eli Bendersky2013-01-251-4/+5
| | | | | | | | | | | | | | | | | | | | | (defined by the x32 ABI) mode, in which case its pointers are 32-bits in size. This knowledge is also added to X86RegisterInfo that now returns the appropriate registers in getPointerRegClass. There are many outcomes to this change. In order to keep the patches separate and manageable, we start by focusing on some simple testable cases. The patch adds a test with passing a pointer to a function - focusing on the difference between the two data models for x86-64. Another test is added for handling of 'sret' arguments (and functionality is added in X86ISelLowering to make it work). A note on naming: the "x32 ABI" document refers to the AMD64 architecture (in LLVM it's distinguished by being is64Bits() in the x86 subtarget) with two variations: the LP64 (default) data model, and the ILP32 data model. This patch adds predicates to the subtarget which are consistent with this naming scheme. llvm-svn: 173503
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-3/+3
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Remove the Function::getFnAttributes method in favor of using the AttributeSetBill Wendling2012-12-301-1/+2
| | | | | | | | | directly. This is in preparation for removing the use of the 'Attribute' class as a collection of attributes. That will shift to the AttributeSet class instead. llvm-svn: 171253
* MC: Add MCInstrDesc::mayAffectControlFlow() method.Jim Grosbach2012-12-191-3/+5
| | | | | | | | | MC disassembler clients (LLDB) are interested in querying if an instruction may affect control flow other than by virtue of being an explicit branch instruction. For example, instructions which write directly to the PC on some architectures. llvm-svn: 170610
* Rename the 'Attributes' class to 'Attribute'. It's going to represent a ↵Bill Wendling2012-12-191-1/+1
| | | | | | single attribute in the future. llvm-svn: 170502
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