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* Fix the macro fusion table for X86 according to Intel optimizationShengchen Kan2019-12-051-171/+12
| | | | | | manual and add function isMacroFused Differential Revision: https://reviews.llvm.org/D70999
* [X86] Merge the different Jcc instructions for each condition code into ↵Craig Topper2019-04-051-17/+21
| | | | | | | | | | | | | | | | | | | | | single instructions that store the condition code as an operand. Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon Reviewed By: RKSimon Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60228 llvm-svn: 357802
* [X86MacroFusion] Handle branch fusion (AMD CPUs).Clement Courbet2019-03-281-53/+98
| | | | | | | | | | | | | | | | | | Summary: This adds a BranchFusion feature to replace the usage of the MacroFusion for AMD CPUs. See D59688 for context. Reviewers: andreadb, lebedev.ri Subscribers: hiraditya, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59872 llvm-svn: 357171
* [X86] Enable 8-bit OR with disjoint bits to convert to LEACraig Topper2019-03-051-0/+2
| | | | | | | | We already support 8-bits adds in convertToThreeAddress. But we can also support 8-bit OR if the bits are disjoint. We already do this for 16/32/64. Differential Revision: https://reviews.llvm.org/D58863 llvm-svn: 355423
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [X86] Remove the AL/AX/EAX/RAX short immediate forms from the macro fusion ↵Craig Topper2018-08-111-18/+0
| | | | | | | | shouldScheduleAdjacent. NFC These instructions are only created by the backend during MCInst lowering. llvm-svn: 339499
* [X86] Add the mem-reg form of CMP to the macro fusion shouldScheduleAdjacent.Craig Topper2018-08-111-0/+4
| | | | | | Unlike the other arithmetic instructions the mem-reg form of compare is just a load and not a RMW operation. According to the Intel optimization manual, this form is also supported by macro fusion. llvm-svn: 339498
* [X86] Remove ADD8mi and ADDmr from the macro fusion shouldScheduleAdjacent.Craig Topper2018-08-111-2/+0
| | | | | | The are RMW of memory operations. They aren't eligible for macro fusion. llvm-svn: 339497
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-1/+1
| | | | | | | | | | | | | | | | We've been running doxygen with the autobrief option for a couple of years now. This makes the \brief markers into our comments redundant. Since they are a visual distraction and we don't want to encourage more \brief markers in new code either, this patch removes them all. Patch produced by for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done Differential Revision: https://reviews.llvm.org/D46290 llvm-svn: 331272
* [X86] Avoid using high register trick for test instructionAmaury Sechet2018-01-311-1/+0
| | | | | | | | | | | | | Summary: It seems it's main effect is to create addition copies when values are inr register that do not support this trick, which increase register pressure and makes the code bigger. Reviewers: craig.topper, niravd, spatel, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42646 llvm-svn: 323888
* Revert "[X86] Avoid using high register trick for test instruction"Eric Liu2018-01-301-0/+1
| | | | | | This reverts commit r323690. This causes crash in llc. See the original commit thread for details. llvm-svn: 323761
* [X86] Avoid using high register trick for test instructionAmaury Sechet2018-01-291-1/+0
| | | | | | | | | | | | | | | Summary: It seems it's main effect is to create addition copies when values are inr register that do not support this trick, which increase register pressure and makes the code bigger. The main noteworthy regression I was able to observe was pattern of the type (setcc (trunc (and X, C)), 0) where C is such as it would benefit from the hi register trick. To prevent this, a new pattern is added to materialize such pattern using a 32 bits test. This has the added benefit of working with any constant that is materializable as a 32bits immediate, not just the ones that can leverage the high register trick, as demonstrated by the test case in test-shrink.ll using the constant 2049 . Reviewers: craig.topper, niravd, spatel, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42646 llvm-svn: 323690
* Recover some overzealously removed includes.Michael Zolotukhin2017-12-131-0/+1
| | | | llvm-svn: 320648
* Remove redundant includes from lib/Target/X86.Michael Zolotukhin2017-12-131-1/+0
| | | | llvm-svn: 320636
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-1/+1
| | | | | | | | This header includes CodeGen headers, and is not, itself, included by any Target headers, so move it into CodeGen to match the layering of its implementation. llvm-svn: 317647
* [X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMemCraig Topper2017-10-011-4/+4
| | | | | | | | | | | | | | | | | | | Summary: Intel documentation shows the memory operand as the first operand. But we currently treat it as the second operand. Conceptually the order doesn't matter since it doesn't write memory. We have aliases to parse with the operands in either order and the isel matching is commutable. For the register&register form order does matter for the assembly parser. PR22995 was previously filed and fixed by changing the register&register form from MRMSrcReg to MRMDestReg to match gas. Ideally the memory form should match by using MRMDestMem. I believe this supercedes D38025 which was trying to switch the register&register form back to pre-PR22995. Reviewers: aymanmus, RKSimon, zvi Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38120 llvm-svn: 314639
* [X86] Provide a separate feature bit for macro fusion support instead of ↵Craig Topper2017-08-301-4/+2
| | | | | | | | | | | | | | | | | | | | | basing it on the AVX flag Summary: Currently we determine if macro fusion is supported based on the AVX flag as a proxy for the processor being Sandy Bridge". This is really strange as now AMD supports AVX. It also means if user explicitly disables AVX we disable macro fusion. This patch adds an explicit macro fusion feature. I've also enabled for the generic 64-bit CPU (which doesn't have AVX) This is probably another candidate for being in the MI layer, but for now I at least wanted to correct the overloading of the AVX feature. Reviewers: spatel, chandlerc, RKSimon, zvi Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37280 llvm-svn: 312097
* Recommit rL305677: [CodeGen] Add generic MacroFusion passFlorian Hahn2017-06-191-85/+16
| | | | | | | | | | | | | Use llvm::make_unique to avoid ambiguity with MSVC. This patch adds a generic MacroFusion pass, that is used on X86 and AArch64, which both define target-specific shouldScheduleAdjacent functions. This generic pass should make it easier for other targets to implement macro fusion and I intend to add macro fusion for ARM shortly. Differential Revision: https://reviews.llvm.org/D34144 llvm-svn: 305690
* Revert r305677 [CodeGen] Add generic MacroFusion pass.Florian Hahn2017-06-191-16/+85
| | | | | | This causes Windows buildbot failures do an ambiguous call. llvm-svn: 305681
* [CodeGen] Add generic MacroFusion pass.Florian Hahn2017-06-191-85/+16
| | | | | | | | | | | | | | | | | | Summary: This patch adds a generic MacroFusion pass, that is used on X86 and AArch64, which both define target-specific shouldScheduleAdjacent functions. This generic pass should make it easier for other targets to implement macro fusion and I intend to add macro fusion for ARM shortly. Reviewers: craig.topper, evandro, t.p.northover, atrick, MatzeB Reviewed By: MatzeB Subscribers: atrick, aemerson, mgorny, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34144 llvm-svn: 305677
* Sink accessing TII to fix release Werror builds.Eric Christopher2017-03-101-5/+3
| | | | llvm-svn: 297507
* [AArch64, X86] Additional debug information for MacroFusionEvandro Menezes2017-03-101-2/+6
| | | | | | | | In order to make it easier to parse information about the performance of MacroFusion, this patch adds the function and the instruction names to the debug output of this pass. llvm-svn: 297504
* [AArch64, X86] Add statistics for the MacroFusion passEvandro Menezes2017-02-211-0/+4
| | | | llvm-svn: 295777
* [AArch64, X86] Guard against both instrs being wild cardsEvandro Menezes2017-02-211-6/+7
| | | | | | If both instrs are wild cards, the result can be a crash. llvm-svn: 295776
* [X86] Prefer static_cast<> to C-style cast. NFCI.Davide Italiano2017-02-191-3/+5
| | | | llvm-svn: 295617
* [X86] Fix enumeral/non-enumeral conditional expression warning.Simon Pilgrim2017-02-191-4/+4
| | | | | | gcc only allows you to mix enums / ints if they have the same signedness. llvm-svn: 295586
* *MacroFusion.cpp: Suppress warnings to eliminate \param(s). [-Wdocumentation]NAKAMURA Takumi2017-02-011-1/+1
| | | | llvm-svn: 293744
* [CodeGen] Move MacroFusion to the targetEvandro Menezes2017-02-011-0/+262
This patch moves the class for scheduling adjacent instructions, MacroFusion, to the target. In AArch64, it also expands the fusion to all instructions pairs in a scheduling block, beyond just among the predecessors of the branch at the end. Differential revision: https://reviews.llvm.org/D28489 llvm-svn: 293737
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