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path: root/llvm/lib/Target/X86/X86MCInstLower.cpp
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* Decouple MCInstBuilder from the streamer per Eli's request.Benjamin Kramer2012-11-261-17/+14
| | | | llvm-svn: 168597
* Add MCInstBuilder, a utility class to simplify MCInst creation similar to ↵Benjamin Kramer2012-11-261-39/+22
| | | | | | | | MachineInstrBuilder. Simplify some repetitive code with it. No functionality change. llvm-svn: 168587
* Fix setjmp on models with non-Small code model nor non-Static relocation modelMichael Liao2012-10-171-10/+8
| | | | | | | | | | - MBB address is only valid as an immediate value in Small & Static code/relocation models. On other models, LEA is needed to load IP address of the restore MBB. - A minor fix of MBB in MC lowering is added as well to enable target relocation flag being propagated into MC. llvm-svn: 166084
* Move X86MCInstLower class definition into implementation file. It's not ↵Craig Topper2012-10-161-1/+25
| | | | | | needed outside. llvm-svn: 166014
* Move expansion of SETB_C(8/16/32/64)r from MCInstLower to ↵Craig Topper2012-10-051-4/+0
| | | | | | ExpandPostRAPseudos and mark them as pseudos in the td file. llvm-svn: 165302
* Convert V_SETALLONES/AVX_SETALLONES/AVX2_SETALLONES to Post-RA pseudos.Craig Topper2012-08-281-3/+0
| | | | llvm-svn: 162740
* Merge AVX_SET0PSY/AVX_SET0PDY/AVX2_SET0 into a single post-RA pseudo.Craig Topper2012-08-281-3/+0
| | | | llvm-svn: 162738
* Whitespace.Chad Rosier2012-08-011-31/+31
| | | | llvm-svn: 161122
* Use a base register instead of an index register with the local dynamic model.Rafael Espindola2012-06-071-0/+8
| | | | | | Fixes pr13048. llvm-svn: 158158
* Implement the local-dynamic TLS model for x86 (PR3985)Hans Wennborg2012-06-011-6/+31
| | | | | | | | | This implements codegen support for accesses to thread-local variables using the local-dynamic model, and adds a clean-up pass so that the base address for the TLS block can be re-used between local-dynamic access on an execution path. llvm-svn: 157818
* Refactor data-in-code annotations.Jim Grosbach2012-05-181-2/+0
| | | | | | | | | | | | | | | | | | | | | | Use a dedicated MachO load command to annotate data-in-code regions. This is the same format the linker produces for final executable images, allowing consistency of representation and use of introspection tools for both object and executable files. Data-in-code regions are annotated via ".data_region"/".end_data_region" directive pairs, with an optional region type. data_region_directive := ".data_region" { region_type } region_type := "jt8" | "jt16" | "jt32" | "jta32" end_data_region_directive := ".end_data_region" The previous handling of ARM-style "$d.*" labels was broken and has been removed. Specifically, it didn't handle ARM vs. Thumb mode when marking the end of the section. rdar://11459456 llvm-svn: 157062
* Implement initial-exec TLS model for 32-bit PIC x86Hans Wennborg2012-05-111-0/+1
| | | | | | | This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong code here (see the update to test/CodeGen/X86/tls-pie.ll). llvm-svn: 156611
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-2/+2
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* Use the same CALL instructions for Windows as for everything else.Jakob Stoklund Olesen2012-02-161-6/+4
| | | | | | | The different calling conventions and call-preserved registers are represented with regmask operands that are added dynamically. llvm-svn: 150708
* Add support for implicit TLS model used with MS VC runtime.Anton Korobeynikov2012-02-111-1/+3
| | | | | | Patch by Kai Nacke! llvm-svn: 150307
* Convert assert(0) to llvm_unreachable in X86 Target directory.Craig Topper2012-02-051-1/+1
| | | | llvm-svn: 149809
* Ignore register mask operands when lowering instructions to MC.Jakob Stoklund Olesen2012-01-181-0/+3
| | | | | | | This is similar to implicit register operands. MC doesn't understand register liveness and call clobbers. llvm-svn: 148437
* Make X86 instruction selection use 256-bit VPXOR for build_vector of all ↵Craig Topper2012-01-131-0/+1
| | | | | | ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32. llvm-svn: 148108
* Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.Jakob Stoklund Olesen2011-11-291-4/+0
| | | | | | | | | Like V_SET0, these instructions are expanded by ExpandPostRA to xorps / vxorps so they can participate in execution domain swizzling. This also makes the AVX variants redundant. llvm-svn: 145440
* Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled.Craig Topper2011-11-191-0/+1
| | | | llvm-svn: 145004
* This commit introduces two fake instructions MORESTACK_RET andRafael Espindola2011-10-261-0/+16
| | | | | | | | | | | | MORESTACK_RET_RESTORE_R10; which are lowered to a RET and a RET followed by a MOV respectively. Having a fake instruction prevents the verifier from seeing a MachineBasicBlock end with a non-terminator (MOV). It also prevents the rather eccentric case of a MachineBasicBlock ending with RET but having successors nevertheless. Patch by Sanjoy Das. llvm-svn: 143062
* Teach the MC to output code/data region marker labels in MachO and ELF ↵Owen Anderson2011-10-041-1/+3
| | | | | | modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment. llvm-svn: 141135
* Expand the x86 V_SET0* pseudos right after register allocation.Jakob Stoklund Olesen2011-09-291-6/+0
| | | | | | | This also makes it possible to reduce the number of pseudo instructions and get rid of the encoding information. llvm-svn: 140776
* Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly ↵Eli Friedman2011-09-071-0/+12
| | | | | | | | fix some subtle bugs involving passes which check mayStore()). This isn't exactly ideal, but it is good enough for the moment. llvm-svn: 139245
* Codegen allonesvector better while using AVX: vpcmpeqd + vinsertf128Bruno Cardoso Lopes2011-07-251-0/+1
| | | | | | This also fixes PR10452 llvm-svn: 136004
* Rename createAsmInfo to createMCAsmInfo and move registration code to ↵Evan Cheng2011-07-141-1/+1
| | | | | | MCTargetDesc to prepare for next round of changes. llvm-svn: 135219
* Re-commit 131641 with fixes; de-pseudoize MOVSX16rr8 and friends.Stuart Hastings2011-05-201-4/+0
| | | | | | rdar://problem/8614450 llvm-svn: 131746
* Reverting 131641 to investigate 'bot complaint.Stuart Hastings2011-05-191-0/+4
| | | | llvm-svn: 131654
* Revise MOVSX16rr8/MOVZX16rr8 (and rm variants) to no longer beStuart Hastings2011-05-191-4/+0
| | | | | | pseudos. rdar://problem/8614450 llvm-svn: 131641
* Add support for AVX to materialize +0.0 when doing scalar FP.Nate Begeman2010-12-091-0/+2
| | | | llvm-svn: 121415
* Move lowering of TLS_addr32 and TLS_addr64 to X86MCInstLower.Rafael Espindola2010-11-281-1/+65
| | | | llvm-svn: 120263
* tidy up, no functionality change.Chris Lattner2010-11-141-2/+0
| | | | llvm-svn: 119092
* move the pic base symbol stuff up to MachineFunctionChris Lattner2010-11-141-9/+4
| | | | | | | since it is trivial and will be shared between ppc and x86. This substantially simplifies the X86 backend also. llvm-svn: 119089
* simplify getPICBaseSymbol a bit.Chris Lattner2010-11-141-1/+1
| | | | llvm-svn: 119088
* handle X86::EH_RETURN64 and X86::EH_RETURN.Rafael Espindola2010-10-261-0/+17
| | | | llvm-svn: 117378
* reapply: Use the new TB_NOT_REVERSABLE flag instead of specialChris Lattner2010-10-081-3/+9
| | | | | | | | | reapply: reimplement the second half of the or/add optimization. We should now with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things a bit. llvm-svn: 116040
* reapply the patch reverted in r116033:Chris Lattner2010-10-081-0/+8
| | | | | | | | "Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'" With a critical fix: the add pseudos clobber EFLAGS. llvm-svn: 116039
* Revert "Reimplement (part of) the or -> add optimization. Matching 'or' intoDaniel Dunbar2010-10-081-8/+0
| | | | | | 'add'", which seems to have broken just about everything. llvm-svn: 116033
* Revert "reimplement the second half of the or/add optimization. We should now",Daniel Dunbar2010-10-081-9/+3
| | | | | | which depends on r116007, which I am about to revert. llvm-svn: 116031
* reimplement the second half of the or/add optimization. We should nowChris Lattner2010-10-081-3/+9
| | | | | | | | | | only end up emitting LEA instead of OR. If we aren't able to promote something into an LEA, we should never be emitting it as an ADD. Add some testcases that we emit "or" in cases where we used to produce an "add". llvm-svn: 116026
* Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'Chris Lattner2010-10-071-0/+8
| | | | | | | | | | | | | | | | | | | is general goodness because it allows ORs to be converted to LEA to avoid inserting copies. However, this is bad because it makes the generated .s file less obvious and gives valgrind heartburn (tons of false positives in bitfield code). While the general fix should be in valgrind, we can at least try to avoid emitting ADD instructions that *don't* get promoted to LEA. This is more work because it requires introducing pseudo instructions to represents "add that knows the bits are disjoint", but hey, people really love valgrind. This fixes this testcase: https://bugs.kde.org/show_bug.cgi?id=242137#c20 the add r/i cases are coming next. llvm-svn: 116007
* Massive rewrite of MMX: Dale Johannesen2010-09-301-3/+0
| | | | | | | | | | | | | | | | | | | The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
* Check in forgotten file. Should fix build.Dale Johannesen2010-09-081-1/+1
| | | | llvm-svn: 113409
* More fixes for win64:Anton Korobeynikov2010-08-171-2/+4
| | | | | | | | - Do not clobber al during variadic calls, this is AMD64 ABI-only feature - Emit wincall64, where necessary Patch by Cameron Esfahani! llvm-svn: 111289
* Don't attempt to SimplifyShortMoveForm in 64-bit mode.Eli Friedman2010-08-161-9/+13
| | | | llvm-svn: 111182
* Define AVX 128-bit pattern versions of SET0PS/PD.Bruno Cardoso Lopes2010-08-121-2/+5
| | | | llvm-svn: 110937
* Begin to support some vector operations for AVX 256-bit intructions. The longBruno Cardoso Lopes2010-08-121-6/+8
| | | | | | | | | term goal here is to be able to match enough of vector_shuffle and build_vector so all avx intrinsics which aren't mapped to their own built-ins but to shufflevector calls can be codegen'd. This is the first (baby) step, support building zeroed vectors. llvm-svn: 110897
* Handle the pseudo in MCInstLower.Eric Christopher2010-08-051-0/+6
| | | | llvm-svn: 110359
* X86MCInstLower now depends on AsmPrinter being around.Chris Lattner2010-07-221-27/+9
| | | | llvm-svn: 109154
* add some rough support for making mcinst lowering work without anChris Lattner2010-07-211-5/+23
| | | | | | | | asmprinter or mangler around. This is option #B for killing off X86InstrInfo::GetInstSizeInBytes. Option #A (killing "needsexactsize") was sent for consideration to llvmdev. llvm-svn: 109056
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