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* Add explicit keywords.Dan Gohman2008-03-251-1/+1
| | | | llvm-svn: 48801
* Get rid of a pseudo instruction and replace it with subreg based operation ↵Christopher Lamb2008-03-131-9/+1
| | | | | | | on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes. llvm-svn: 48329
* Recommitting parts of r48130. These do not appear to cause the observed ↵Christopher Lamb2008-03-111-0/+8
| | | | | | failures. llvm-svn: 48223
* Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.Evan Cheng2008-03-101-8/+0
| | | | llvm-svn: 48167
* Allow insert_subreg into implicit, target-specific values. Christopher Lamb2008-03-101-0/+8
| | | | | | | Change insert/extract subreg instructions to be able to be used in TableGen patterns. Use the above features to reimplement an x86-64 pseudo instruction as a pattern. llvm-svn: 48130
* Add lock prefix support to x86. Also add the instructions necessary for the ↵Andrew Lenharth2008-03-011-1/+5
| | | | | | atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode. llvm-svn: 47795
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-2/+2
| | | | llvm-svn: 46930
* It's not always safe to fold movsd into xorpd, etc. Check the alignment of ↵Evan Cheng2008-02-081-2/+4
| | | | | | the load address first to make sure it's 16 byte aligned. llvm-svn: 46893
* Simplify the side effect stuff a bit more and make licm/sinkingChris Lattner2008-01-101-1/+1
| | | | | | | | | | | | | | | | both work right according to the new flags. This removes the TII::isReallySideEffectFree predicate, and adds TII::isInvariantLoad. It removes NeverHasSideEffects+MayHaveSideEffects and adds UnmodeledSideEffects as machine instr flags. Now the clients can decide everything they need. I think isRematerializable can be implemented in terms of the flags we have now, though I will let others tackle that. llvm-svn: 45843
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-1/+1
| | | | | | | Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
* remove MachineOpCode typedef.Chris Lattner2008-01-071-1/+1
| | | | llvm-svn: 45679
* Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson2008-01-071-0/+56
| | | | | | Some day I'll get it all moved over... llvm-svn: 45672
* Move some more functionality from MRegisterInfo to TargetInstrInfo.Owen Anderson2008-01-041-0/+9
| | | | llvm-svn: 45603
* Machine LICM will check that operands are defined outside of the loop. AlsoBill Wendling2008-01-021-7/+0
| | | | | | check that register isn't 0 before going further. llvm-svn: 45498
* Move some more instruction creation methods from RegisterInfo into InstrInfo.Owen Anderson2008-01-011-0/+19
| | | | llvm-svn: 45484
* Fix a problem where lib/Target/TargetInstrInfo.h would include and useChris Lattner2008-01-011-1/+1
| | | | | | | | | | a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. llvm-svn: 45475
* Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson2007-12-311-0/+5
| | | | | | Machine-level API cleanup instigated by Chris. llvm-svn: 45470
* If we have a load of a global address that's not modified during theBill Wendling2007-12-301-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | function, then go ahead and hoist it out of the loop. This is the result: $ cat a.c volatile int G; int A(int N) { for (; N > 0; --N) G++; } $ llc -o - -relocation-model=pic _A: ... LBB1_2: # bb movl L_G$non_lazy_ptr-"L1$pb"(%eax), %esi incl (%esi) incl %edx cmpl %ecx, %edx jne LBB1_2 # bb ... $ llc -o - -relocation-model=pic -machine-licm _A: ... movl L_G$non_lazy_ptr-"L1$pb"(%eax), %eax LBB1_2: # bb incl (%eax) incl %edx cmpl %ecx, %edx jne LBB1_2 # bb ... I'm limiting this to the MOV32rm x86 instruction for now. llvm-svn: 45444
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. IBill Wendling2007-12-171-1/+2
| | | | | | | | | based what flag to set on whether it was already marked as "isRematerializable". If there was a further check to determine if it's "really" rematerializable, then I marked it as "mayHaveSideEffects" and created a check in the X86 back-end similar to the remat one. llvm-svn: 45132
* Reverting 44702. It wasn't correct to rename them.Bill Wendling2007-12-081-1/+1
| | | | llvm-svn: 44727
* Renaming:Bill Wendling2007-12-081-1/+1
| | | | | | | isTriviallyReMaterializable -> hasNoSideEffects isReallyTriviallyReMaterializable -> isTriviallyReMaterializable llvm-svn: 44702
* Move getX86RegNum into X86RegisterInfo and use itDuncan Sands2007-08-291-1/+4
| | | | | | | | in the trampoline lowering. Lookup the jump and mov opcodes for the trampoline rather than hard coding them. llvm-svn: 41577
* Revert the earlier change that removed the M_REMATERIALIZABLE machineDan Gohman2007-06-261-1/+1
| | | | | | | | | instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). llvm-svn: 37728
* Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman2007-06-191-1/+1
| | | | | | | | | | with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. llvm-svn: 37644
* Do not treat FP_REG_KILL as terminator in branch analysis (X86).Dale Johannesen2007-06-141-0/+1
| | | | llvm-svn: 37578
* Add a target hook to allow loads from constant pools to be rematerialized, ↵Dan Gohman2007-06-141-0/+1
| | | | | | | | and an implementation for x86. llvm-svn: 37576
* RemoveBranch() and InsertBranch() now returns number of instructions deleted ↵Evan Cheng2007-05-181-4/+4
| | | | | | / inserted. llvm-svn: 37193
* Add support for our first SSSE3 instruction "pmulhrsw".Bill Wendling2007-04-101-1/+4
| | | | llvm-svn: 35869
* Make LABEL a builtin opcode.Jim Laskey2007-01-261-5/+0
| | | | llvm-svn: 33537
* - Fix X86-64 JIT by temporarily disabling code that treats GV address as 32-bitEvan Cheng2006-12-051-2/+2
| | | | | | | | immediate in small code model. The JIT cannot ensure GV's are placed in the lower 4G. - Some preliminary support for large code model. llvm-svn: 32215
* Match TargetInstrInfo changes.Evan Cheng2006-12-011-1/+3
| | | | llvm-svn: 32098
* add another target hook for branch folding.Chris Lattner2006-10-281-0/+1
| | | | llvm-svn: 31262
* Implement support for branch condition reversal.Chris Lattner2006-10-211-0/+5
| | | | llvm-svn: 31099
* Implement branch analysis/xform hooks required by the branch folding pass.Chris Lattner2006-10-201-0/+36
| | | | llvm-svn: 31065
* expose DWARF_LABEL opcode# so the branch folder can update debug info properly.Chris Lattner2006-10-171-0/+5
| | | | llvm-svn: 31024
* remove some dead codeChris Lattner2006-10-131-10/+0
| | | | llvm-svn: 30938
* Committing X86-64 support.Evan Cheng2006-09-081-7/+26
| | | | llvm-svn: 30177
* Fix a build breaker.Evan Cheng2006-05-301-1/+3
| | | | llvm-svn: 28574
* Patches to make the LLVM sources more -pedantic clean. Patch providedChris Lattner2006-05-241-1/+1
| | | | | | by Anton Korobeynikov! This is a step towards closing PR786. llvm-svn: 28447
* ImmMask should be 3 for a two-bit field; Compact X86IIEvan Cheng2006-05-181-3/+2
| | | | llvm-svn: 28381
* Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far ↵Chris Lattner2006-02-021-5/+5
| | | | | | more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
* - Use xor to clear integer registers (set R, 0).Evan Cheng2006-02-011-7/+11
| | | | | | | | - Added a new format for instructions where the source register is implied and it is same as the destination register. Used for pseudo instructions that clear the destination register. llvm-svn: 25872
* Eliminate tabs and trailing spaces.Jeff Cohen2005-07-271-1/+1
| | | | llvm-svn: 22520
* First round of support for doing scalar FP using the SSE2 ISA extension andNate Begeman2005-07-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | XMM registers. There are many known deficiencies and fixmes, which will be addressed ASAP. The major benefit of this work is that it will allow the LLVM register allocator to allocate FP registers across basic blocks. The x86 backend will still default to x87 style FP. To enable this work, you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc. An example before and after would be for: double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i) Sum += P[i]; return Sum; } The inner loop looks like the following: x87: .LBB_foo_1: # no_exit fldl (%esp) faddl (%eax,%ecx,8) fstpl (%esp) incl %ecx cmpl $1000, %ecx #FP_REG_KILL jne .LBB_foo_1 # no_exit SSE2: addsd (%eax,%ecx,8), %xmm0 incl %ecx cmpl $1000, %ecx #FP_REG_KILL jne .LBB_foo_1 # no_exit llvm-svn: 22340
* * Remove trailing whitespaceMisha Brukman2005-04-211-4/+4
| | | | | | * Convert tabs to spaces llvm-svn: 21426
* Teach the code generator that shrd/shld is commutable if it has an immediate.Chris Lattner2005-01-191-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | This allows us to generate this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %EDX, DWORD PTR [%ESP + 8] shld %EDX, %EDX, 2 shl %EAX, 2 ret instead of this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, DWORD PTR [%ESP + 8] mov %EDX, %EAX shrd %EDX, %ECX, 30 shl %EAX, 2 ret Note the magically transmogrifying immediate. llvm-svn: 19686
* Implement the convertToThreeAddress method, add support for inverting JP/JNPChris Lattner2005-01-021-0/+12
| | | | | | branches. llvm-svn: 19247
* Remove a bunch of ad-hoc target-specific flags that were only used by theChris Lattner2004-08-111-20/+5
| | | | | | old asmprinter. llvm-svn: 15660
* Eliminate 3 of the X86 printImplicit* flags.Chris Lattner2004-08-011-10/+1
| | | | llvm-svn: 15398
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