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* Remove explicit enum integer values. They don't appear to be needed, andDan Gohman2009-10-051-17/+17
| | | | | | they make it less convenient to add new entries. llvm-svn: 83308
* It's not legal to fold a load from a narrower stack slot into a wider ↵Evan Cheng2009-09-111-1/+1
| | | | | | | | | | | | instruction. If done, the instruction does a 64-bit load and that's not safe. This can happen we a subreg_to_reg 0 has been coalesced. One exception is when the instruction that folds the load is a move, then we can simply turn it into a 32-bit load from the stack slot. rdar://7170444 llvm-svn: 81494
* Reference to hidden symbols do not have to go through non-lazy pointer in ↵Evan Cheng2009-09-031-7/+1
| | | | | | non-pic mode. rdar://7187172. llvm-svn: 80904
* Add crc32 instruction and intrinsics. Add a new class of prefixEric Christopher2009-08-081-0/+3
| | | | | | | | | bytes for F2 0F 38 and propagate. Add a FIXME for a set of possibilities which correspond to intrinsics already used. New test. llvm-svn: 78508
* Let callers decide the sub-register index on the def operand of ↵Evan Cheng2009-07-161-1/+2
| | | | | | | | rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
* Move load / store folding alignment require into the table(s).Evan Cheng2009-07-151-7/+8
| | | | llvm-svn: 75749
* Undo my brain cramp.Evan Cheng2009-07-101-6/+0
| | | | llvm-svn: 75290
* CMOVxx doesn't swap operands which it's commuted.Evan Cheng2009-07-101-0/+6
| | | | llvm-svn: 75266
* add a predicate to determine if a global var reference requires aChris Lattner2009-07-101-0/+16
| | | | | | PIC-base to be added in. llvm-svn: 75238
* change isGlobalStubReference to take target flags instead of a MachineOperand.Chris Lattner2009-07-101-6/+5
| | | | llvm-svn: 75236
* add a new predicate method that says whether a GlobalValue Chris Lattner2009-07-101-1/+27
| | | | | | | MachineOperand is a reference to a stub, not a reference to the global variable itself. Look no context needed! llvm-svn: 75233
* move reasoning about darwin $non_lazy_ptr stubs from asmprinter intoChris Lattner2009-07-091-0/+20
| | | | | | isel. llvm-svn: 75117
* make isel decide whether to emit $stub's on darwin instead of asmprinter.Chris Lattner2009-07-091-0/+5
| | | | llvm-svn: 75107
* move handling of dllimport linkage in isel, not in asmprinter.Chris Lattner2009-07-091-0/+6
| | | | llvm-svn: 75086
* Move all the TLS processing logic into isel, don't do it in asmprinter at all.Chris Lattner2009-06-261-3/+61
| | | | llvm-svn: 74327
* start adding logic in isel to determine asm printer semantics, step N of M.Chris Lattner2009-06-261-1/+11
| | | | llvm-svn: 74246
* Use target-specific machine operand flags to eliminate a gross hackChris Lattner2009-06-251-1/+12
| | | | | | from the asmprinter. llvm-svn: 74184
* Re-apply 68552.Rafael Espindola2009-04-081-2/+9
| | | | | | Tested by bootstrapping llvm-gcc and using that to build llvm. llvm-svn: 68645
* Temporarily revert r68552. This was causing a failure in the self-hosting LLVMBill Wendling2009-04-071-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | builds. --- Reverse-merging (from foreign repository) r68552 into '.': U test/CodeGen/X86/tls8.ll U test/CodeGen/X86/tls10.ll U test/CodeGen/X86/tls2.ll U test/CodeGen/X86/tls6.ll U lib/Target/X86/X86Instr64bit.td U lib/Target/X86/X86InstrSSE.td U lib/Target/X86/X86InstrInfo.td U lib/Target/X86/X86RegisterInfo.cpp U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86CodeEmitter.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86InstrInfo.h U lib/Target/X86/X86ISelDAGToDAG.cpp U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h U lib/Target/X86/X86ISelLowering.h U lib/Target/X86/X86InstrInfo.cpp U lib/Target/X86/X86InstrBuilder.h U lib/Target/X86/X86RegisterInfo.td llvm-svn: 68560
* Reduce code duplication on the TLS implementation.Rafael Espindola2009-04-071-2/+9
| | | | | | | | | | This introduces a small regression on the generated code quality in the case we are just computing addresses, not loading values. Will work on it and on X86-64 support. llvm-svn: 68552
* Have only one definition of X86AddrNumOperands.Rafael Espindola2009-03-281-0/+2
| | | | llvm-svn: 67949
* Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nastyEvan Cheng2009-02-091-1/+2
| | | | | | | | suprise to some callers, e.g. register coalescer. For now, add an parameter that tells AnalyzeBranch whether it's safe to modify the mbb. A better solution is out there, but I don't have time to deal with it right now. llvm-svn: 64124
* Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.Evan Cheng2009-02-061-2/+0
| | | | llvm-svn: 63938
* Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's ↵Evan Cheng2009-02-061-4/+3
| | | | | | safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook. llvm-svn: 63936
* Change TargetInstrInfo::isMoveInstr to return source and destination ↵Evan Cheng2009-01-201-5/+6
| | | | | | sub-register indices as well. llvm-svn: 62600
* X86_COND_C and X86_COND_NC are alternate mnemonics forDan Gohman2009-01-071-5/+3
| | | | | | X86_COND_B and X86_COND_AE, respectively. llvm-svn: 61835
* Tidy up #includes, deleting a bunch of unnecessary #includes.Dan Gohman2009-01-051-2/+2
| | | | llvm-svn: 61715
* Split foldMemoryOperand into public non-virtual and protected virtualDan Gohman2008-12-031-12/+12
| | | | | | | parts, and add target-independent code to add/preserve MachineMemOperands. llvm-svn: 60488
* Generate something sensible for an [SU]ADDO op when the overflow/carry flag isBill Wendling2008-11-261-3/+5
| | | | | | | | | | | | | | | the conditional for the BRCOND statement. For instance, it will generate: addl %eax, %ecx jo LOF instead of addl %eax, %ecx ; About 10 instructions to compare the signs of LHS, RHS, and sum. jl LOF llvm-svn: 60123
* Add more const qualifiers. This fixes build breakage from r59540.Dan Gohman2008-11-181-3/+3
| | | | llvm-svn: 59542
* For now, don't split live intervals around x87 stack register barriers. ↵Evan Cheng2008-10-271-0/+5
| | | | | | FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them. llvm-svn: 58230
* Optimized FCMP_OEQ and FCMP_UNE for x86.Dan Gohman2008-10-211-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
* getX86RegNum has long been moved to X86RegisterInfo.Evan Cheng2008-10-171-1/+0
| | | | llvm-svn: 57691
* Const-ify several TargetInstrInfo methods.Dan Gohman2008-10-161-5/+6
| | | | llvm-svn: 57622
* Add ability to override segment (mostly for code emitter purposes).Anton Korobeynikov2008-10-111-1/+8
| | | | llvm-svn: 57380
* Switch the MachineOperand accessors back to the short names likeDan Gohman2008-10-031-8/+8
| | | | | | isReg, etc., from isRegister, etc. llvm-svn: 57006
* Move the GlobalBaseReg field out of X86ISelDAGToDAG.cppDan Gohman2008-09-301-3/+4
| | | | | | | | and X86FastISel.cpp into X86MachineFunction.h, so that it can be shared, instead of having each selector keep track of its own. llvm-svn: 56825
* Move the code for initializing the global base reg out ofDan Gohman2008-09-231-0/+5
| | | | | | | X86ISelDAGToDAG.cpp and into X86InstrInfo.cpp. This will allow it to be reused by FastISel. llvm-svn: 56494
* Backing out 55521. Not safe.Evan Cheng2008-08-291-5/+0
| | | | llvm-svn: 55548
* Swap fp comparison operands and change predicate to allow load folding.Evan Cheng2008-08-281-0/+5
| | | | llvm-svn: 55521
* Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy ↵Owen Anderson2008-08-261-1/+1
| | | | | | | | | requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
* Convert uses of std::vector in TargetInstrInfo to SmallVector. This change ↵Owen Anderson2008-08-141-3/+4
| | | | | | had to be propoagated down into all the targets and up into all clients of this API. llvm-svn: 54802
* Pool-allocation for MachineInstrs, MachineBasicBlocks, andDan Gohman2008-07-071-3/+4
| | | | | | | | | | | MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
* Make LiveVariables even more optional, by making it optional in the call to ↵Owen Anderson2008-07-021-1/+1
| | | | | | | | TargetInstrInfo::convertToThreeAddressInstruction Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place. llvm-svn: 53058
* Make intel asmprinter child of generic asmprinter, not x86 shared asm ↵Anton Korobeynikov2008-06-281-0/+17
| | | | | | printer. This leads to some code duplication, which will be resolved later. llvm-svn: 52858
* Add option to commuteInstruction() which forces it to create a new ↵Evan Cheng2008-06-161-1/+1
| | | | | | (commuted) instruction. llvm-svn: 52308
* Change target-specific classes to use more precise static types.Dan Gohman2008-05-141-1/+1
| | | | | | | This eliminates the need for several awkward casts, including the last dynamic_cast under lib/Target. llvm-svn: 51091
* Constify the machine instruction passed into theBill Wendling2008-05-121-1/+1
| | | | | | "is{Trivially,Really}ReMaterializable" methods. llvm-svn: 51001
* Infrastructure for getting the machine code size of a function and an ↵Nicolas Geoffray2008-04-161-0/+15
| | | | | | instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
* Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.Evan Cheng2008-03-311-0/+4
| | | | llvm-svn: 48995
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